Camille Diou
Orcid: 0000-0002-6887-1895
According to our database1,
Camille Diou
authored at least 20 papers
between 1999 and 2021.
Collaborative distances:
Collaborative distances:
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Bibliography
2021
Ann. des Télécommunications, 2021
2019
Genetic algorithms for scheduling in a CPU/FPGA architecture with heterogeneous communication delays.
Comput. Ind. Eng., 2019
2017
Formal Proof of the Dependable Bypassing Routing Algorithm Suitable for Adaptive Networks on Chip QnoC Architecture.
Syst., 2017
A comparison of two metaheuristic algorithms for scheduling problem on a heterogeneous CPU/FPGA architecture with communication delays.
Proceedings of the 4th International Conference on Control, 2017
2015
LOS/NLOS Identification Based on Stable Distribution Feature Extraction and SVM Classifier for UWB On-Body Communications.
J. Ubiquitous Syst. Pervasive Networks, 2015
2014
Proceedings of the International Conference on Control, 2014
2011
Int. J. Reconfigurable Comput., 2011
2010
Behavioral modeling and C-VHDL co-simulation of Network on Chip on FPGA for Education.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
A Self-Checking HW Journal for a Fault Tolerant Processor Architecture.
Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, 2010
2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2007
Stack processor architecture and development methods suitable for dependable applications.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
CodeRAKE: a new small-area scalable architecture for the multi-user/multi-code RAKE receiver.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
2002
Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications.
Proceedings of the 2002 Design, 2002
2001
Proceedings of the Field-Programmable Logic and Applications, 2001
Proceedings of 8th IEEE International Conference on Emerging Technologies and Factory Automation, 2001
2000
Proceedings of the 2000 International Conference on Image Processing, 2000
1999
Implementation of a Wavelet Transform Architecture for Image Processing.
Proceedings of the VLSI: Systems on a Chip, 1999