Calvin Deutschbein

Orcid: 0000-0003-1354-7200

According to our database1, Calvin Deutschbein authored at least 14 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Isadora: automated information-flow property generation for hardware security verification.
J. Cryptogr. Eng., November, 2023

Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

2022
Toward Hardware Security Property Generation at Scale.
IEEE Secur. Priv., 2022

2021
Mining Secure Behavior of Hardware Designs.
PhD thesis, 2021

End-to-End Automated Exploit Generation for Processor Security Validation.
IEEE Des. Test, 2021

Mining Secure Behavior of Hardware Designs.
CoRR, 2021

A Methodology For Creating Information Flow Specifications of Hardware Designs.
CoRR, 2021

Isadora: Automated Information Flow Property Generation for Hardware Designs.
Proceedings of the ASHES@CCS 2021: Proceedings of the 5th Workshop on Attacks and Solutions in Hardware Security, 2021

2020
Evaluating Security Specification Mining for a CISC Architecture.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

2019
Multi-core cyclic executives for safety-critical systems.
Sci. Comput. Program., 2019

2018
Mining Security Critical Linear Temporal Logic Specifications for Processors.
Proceedings of the 19th International Workshop on Microprocessor and SOC Test and Verification, 2018

End-to-End Automated Exploit Generation for Validating the Security of Processor Designs.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

2016
Preemptive Uniprocessor EDF Schedulability Analysis with Preemption Costs Considered.
Proceedings of the 2016 IEEE Real-Time Systems Symposium, 2016

2014
Performance and energy limits of a processor-integrated FFT accelerator.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014


  Loading...