C. W. Cheng

According to our database1, C. W. Cheng authored at least 9 papers between 1993 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1995
2000
2005
2010
2015
2020
0
1
2
3
4
5
1
4
1
1
2

Legend:

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In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2024
A Novel Chalcogenide Based CuGeSe Selector Only Memory (SOM) for 3D Xpoint and 3D Vertical Memory Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

State-Independent Low Resistance Drift SiSbTe Phase Change Memory for Analog In-Memory Computing Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

AsSeGeS and GeN Heterostructures for Superior OTS Performance.
Proceedings of the IEEE International Memory Workshop, 2024

A Novel Program-verify Free and Low Drift Multilevel Operation on Cross-point OTS-PCM for In-Memory Computing Application.
Proceedings of the IEEE International Memory Workshop, 2024

2023
A Comprehensive Study on the Pillar Size of OTS-PCM Memory with an Optimized Process and Scaling Trends Down to Sub-10 nm for SCM Applications.
Proceedings of the IEEE International Memory Workshop, 2023

2022
Endurance Evaluation on OTS-PCM Device using Constant Current Stress Scheme.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2005
A PBX-based approach for telecommunication number portability service.
Proceedings of the ICETE 2005, 2005

An organization-based cache mechanism for supporting pcs number portability service.
Proceedings of the ICETE 2005, 2005

1993
A nonlinear 3D MOSFET table for VLSI circuit simulation.
Microprocess. Microprogramming, 1993


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