C. P. Ravikumar

According to our database, C. P. Ravikumar authored at least 112 papers between 1987 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Industrial Practices in Low-Power Robust Design.

C. P. Ravikumar

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

2018

Architectural Optimization of Hierarchically Organized Wireless Sensor Networks for Energy, Cost, and Security.

Ananya Ravikumar, C. P. Ravikumar

J. Low Power Electron., 2018

2016

Smart and Fault-Tolerant LED-Based Street Lamps.

C. P. Ravikumar

J. Low Power Electron., 2016

2013

Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation

Namita Sharma, Vineet Sahula, C. P. Ravikumar

CoRR, 2013

2012

On-chip memory architecture exploration framework for DSP processor-based embedded system on chip.

T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar

ACM Trans. Embed. Comput. Syst., 2012

2008

Test Strategies for Low-Power Devices.

C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen

J. Low Power Electron., 2008

A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction.

V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti

J. Low Power Electron., 2008

Memory Architecture Exploration Framework for Cache Based Embedded SOC.

T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models.

Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

A critical-path-aware partial gating approach for test power reduction.

Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar

ACM Trans. Design Autom. Electr. Syst., 2007

Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers.

Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Low-Power Hierarchical Scan Test for Multiple Clock Domains.

Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy

J. Low Power Electron., 2007

Conference Reports.

C. P. Ravikumar, Jari Nurmi

IEEE Des. Test Comput., 2007

Variation-Tolerant, Power-Safe Pattern Generation.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

IEEE Des. Test Comput., 2007

Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip.

T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test.

V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti

Proceedings of the 2007 IEEE International Test Conference, 2007

A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

Proceedings of the 2007 IEEE International Test Conference, 2007

Interactive presentation: On power-profiling and pattern generation for power-safe scan tests.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides.

Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian

Proceedings of the 16th Asian Test Symposium, 2007

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip.

T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores.

V. R. Devanathan, C. P. Ravikumar, V. Kamakoti

J. Low Power Electron., 2006

Conference Reports.

Subhasish Mitra, Ondrej Novák, Hana Kubátová, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar

IEEE Des. Test Comput., 2006

2005

At-Speed Transition Fault Testing With Low Speed Scan Enable.

Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

A Framework for Distributed and Hierarchical Design-for-Test.

C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer.

Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Enhanced launch-off-capture transition fault testing.

Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Partial Gating Optimization for Power Reduction During Test Application.

Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

A self-checking signature scheme for checking backdoor security attacks in Internet.

Mohammed Fadle Abdulla, C. P. Ravikumar

J. High Speed Networks, 2004

Multiprocessor Architectures for Embedded System-on-chip Applications.

C. P. Ravikumar

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures.

Aman Kokrady, C. P. Ravikumar

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

A Holistic Parallel and Hierarchical Approach towards Design-For-Test.

C. P. Ravikumar, Graham Hetherington

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003

Mutual Testing based on Wavelet Transforms.

C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Optimal Code and Data Layout in Embedded Systems.

T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Static Verification of Test Vectors for IR Drop Failure.

Aman Kokrady, C. P. Ravikumar

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

2002

Improvement of ASIC Design Processes.

Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Divide-and-Conquer IDDQ Testing for Core-Based System Chips.

C. P. Ravikumar, Rahul Kumar

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment.

Rahul Kumar, C. P. Ravikumar

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

An Evolutionary Scheme for Cosynthesis of Real-Time Systems.

Shampa Chakraverty, C. P. Ravikumar, D. Roy Choudhuri

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Measuring the Quality of Web Search Results.

Mirza Mohd. Sufyan Beg, C. P. Ravikumar

Proceedings of the 6th Joint Conference on Information Science, 2002

2001

Distributed Fault Simulation Algorithms on Parallel Virtual Machine.

C. P. Ravikumar, Vikas Jain, Anurag Dod

VLSI Design, 2001

Estimating Crosstalk From Vlsi Layouts.

V. Sankara Subramanian, C. P. Ravikumar

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes.

Vineet Sahula, C. P. Ravikumar

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Software Power Optimizations In An Embedded System.

Vishal Dalal, C. P. Ravikumar

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000

A scheme for multiple on-chip signature checking for embedded SRAMS.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

J. Syst. Archit., 2000

Efficient Implementation of ADPCM Codec.

Anil Sharma, C. P. Ravikumar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems.

C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

A Stochastic Framework for Co-synthesis of Real-Time Systems.

Shampa Chakraverty, C. P. Ravikumar

Proceedings of the Languages, 2000

Functional Testing of Microprocessors with Graded Fault Coverage.

Rajesh Kannah, C. P. Ravikumar

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

High-Performance Cluster Computing. Volume 1: Architecutes and Systems. Volume 2: Programming and Applications.

C. P. Ravikumar

Parallel Distributed Comput. Pract., 1999

A functional-level testability measure for register-level circuits and its estimation.

C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal

Microprocess. Microsystems, 1999

Built-in Self Test Based on Multiple On-Chip Signature Checking.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

J. Electron. Test., 1999

Improving the Diagnosability of Digital Circuits.

C. P. Ravikumar, Manish Sharma, R. K. Patney

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Hierarchical Delay Fault Simulation.

C. P. Ravikumar, Ajay Mittal

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Design of WDM Networks for Delay-Bound Multicasting.

C. P. Ravikumar, Meeta Sharma, Prachi Jain

Proceedings of the High Performance Computing, 1999

Efficient Algorithms for Delay Bounded Multicast Tree Generation for Multimedia Applications.

Nishit Narang, Girish Kumar, C. P. Ravikumar

Proceedings of the High Performance Computing, 1999

Design Issues in Synthesis of Reusable Cores.

Rohit Sharma, C. P. Ravikumar

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems.

C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Testability-Driven Layout of Combinational Circuits.

C. P. Ravikumar, Nikhil Sharma

VLSI Design, 1998

SCOAP-based Testability Analysis from Hierarchical Netlists.

C. P. Ravikumar, Hemant Joshi

VLSI Design, 1998

Parallel Methods for Vlsi Layout Design.

Roman Trobec, C. P. Ravikumar

IEEE Concurr., 1998

Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

J. Electron. Test., 1998

Source-based delay-bounded multicasting in multimedia networks.

C. P. Ravikumar, Rajneesh Bajpai

Comput. Commun., 1998

Freedom: Statistical Behavioral Estimation of System Energy and Power.

Suhrid A. Wadekar, Alice C. Parker, C. P. Ravikumar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Synthesis of Testable RTL Designs.

C. P. Ravikumar, Sumit Gupta, Akshay Jajoo

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

An Evolutionary Approach to System Redesign.

Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

On-Chip Signature Checking for Embedded Memories.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Hybrid Testing Schemes Based on Mutual and Signature Testing.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Performance-driven design and redesign of high-speed local area networks.

C. P. Ravikumar, Dilip R. Pandit, Anubhav Mishra

Proceedings of the 5th International Conference On High Performance Computing, 1998

Efficient algorithms for delay-bounded minimum cost path problem in communication networks.

Girish Kumar, Nishit Narang, C. P. Ravikumar

Proceedings of the 5th International Conference On High Performance Computing, 1998

Adaptive Routing Based on Deadlock Recovery.

Nidhi Agrawal, C. P. Ravikumar

Proceedings of the Euro-Par '98 Parallel Processing, 1998

Evaluating BIST Architectures for Low Power.

C. P. Ravikumar, N. Satya Prasad

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

Adaptive routing in k-ary n-cubes using incomplete diagnostic information.

C. P. Ravikumar, C. S. Panda

Microprocess. Microsystems, 1997

Parallelization of symmetry detection algorithms on a network of workstations.

R. Parthiban, C. P. Ravikumar, R. Kakarala, J. Sivaswamy

Microprocess. Microsystems, 1997

Hierarchical Delay Test Generation.

C. P. Ravikumar, Nitin Agrawal, Parul Agarwal

J. Electron. Test., 1997

Kautz graphs as attractive logical topologies in multihop lightwave networks.

C. P. Ravikumar, Tarun Rai, Varun Verma

Comput. Commun., 1997

Faster Fault Simulation Through Distributed Computing.

C. P. Ravikumar, Vikas Jain, Anurag Dod

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

A Graph-Theoretic Approach for Register File Based Synthesis.

C. P. Ravikumar, R. Aggarwal, C. Sharma

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Rapid Synthesis of Multi-Chip Systems.

Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Efficient Implementation of Multiple On-Chip Signature Checking.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

An Euler Path Based Technique for Deadlock-free Multicasting.

Nidhi Agrawal, C. P. Ravikumar

Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

Distributed delay constrained multicast path setup algorithm for high speed networks.

Ramnik Bajaj, C. P. Ravikumar, Suresh Chandra

Proceedings of the Fourth International on High-Performance Computing, 1997

1996

TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis.

C. P. Ravikumar, Vikram Saxena

VLSI Design, 1996

Parallel search-and-learn techniques and graph coloring.

C. P. Ravikumar, R. Aggarwal

Knowl. Based Syst., 1996

Fault-tolerant routing in multiply twisted cube topology.

Nidhi Agrawal, C. P. Ravikumar

J. Syst. Archit., 1996

Synthesis of Testable Pipelined Datapaths Using Genetic Search.

C. P. Ravikumar, Vikram Saxena

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Genetic Algorithms for Scan Path Design.

C. P. Ravikumar, Rajamani Rajarajan

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Estimation of Power from Module-level Netlists.

C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Novel BIST Architecture With Built-in Self Check.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A genetic algorithm for assembling optical computers using faulty optical arrays.

C. P. Ravikumar, Augustine R. Thomas, Abhay Gupta

Proceedings of the 3rd International Conference on High Performance Computing, 1996

Efficient Delay Test Generation for Modular Circuits.

Nidhi Agrawal, Parul Agarwal, C. P. Ravikumar

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

SHARP: A shape recognition system and its parallel implementation.

C. P. Ravikumar, Rajender Sethi

Microprocess. Microsystems, 1995

Heuristic and neural algorithms for mapping tasks to a reconfigurable array.

C. P. Ravikumar, Naresh Vedi

Microprocess. Microprogramming, 1995

HISCOAP: a hierarchical testability analysis tool.

C. P. Ravikumar, Hemant Joshi

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A STAFAN-like functional testability measure for register-level circuits.

C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing.

C. P. Ravikumar, Haroon Rasheed

VLSI Design, 1994

Parallel search-and-learn technique for solving large scale travelling-salesperson problems.

C. P. Ravikumar

Knowl. Based Syst., 1994

Simulated Annealing for Target-Oriented Scan.

C. P. Ravikumar, Haroon Rasheed

Proceedings of the Seventh International Conference on VLSI Design, 1994

Star-Graph based multistage interconnection network for ATM switch fabric.

C. P. Ravikumar, G. Manimaran

Proceedings of the Sixth IEEE Symposium on Parallel and Distributed Processing, 1994

1993

Solving VLSI physical design problems on a vector machine.

C. P. Ravikumar

Comput. Aided Des., 1993

A Parallel Search-and-Learn Technique for Solving Large Scale TSP.

C. P. Ravikumar

Proceedings of the Fifth International Conference on Tools with Artificial Intelligence, 1993

Incomplete Star Graph: An Economical Fault-tolerant Interconnection Network.

C. P. Ravikumar, A. Kuchlous, G. Manimaran

Proceedings of the 1993 International Conference on Parallel Processing, 1993

1992

Parallel techniques for solving large scale travelling salesperson problems.

C. P. Ravikumar

Microprocess. Microsystems, 1992

Interval partition with bounded overlap.

C. P. Ravikumar

Comput. Aided Des., 1992

Solving Physical Design Problems on a Vector Machine.

C. P. Ravikumar

Proceedings of the Fifth International Conference on VLSI Design, 1992

1991

VYUHA: A detailed router for multiple routing models.

C. P. Ravikumar, Sarma Sastry

Integr., 1991

1990

Performance improvement of simulated annealing algorithms.

C. P. Ravikumar, Lalit M. Patnaik

Comput. Syst. Sci. Eng., 1990

1989

A hardware accelerator for hierarchical VLSI routing.

C. P. Ravikumar, Sarma Sastry

Integr., 1989

Parallel Placement on Hypercube Architecture.

C. P. Ravikumar, Sarma Sastry

Proceedings of the International Conference on Parallel Processing, 1989

1988

Parallel Placement on Reduced Array Architecture.

C. P. Ravikumar, Sarma Sastry

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

An Architecture for CSP and Its Simulation.

C. P. Ravikumar, Lalit M. Patnaik

Proceedings of the International Conference on Parallel Processing, 1987