C. L. Liu

According to our database, C. L. Liu authored at least 132 papers between 1964 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2012

I attended the nineteenth design automation conference.

C. L. Liu

Proceedings of the International Symposium on Physical Design, 2012

2005

The High Walls have Crumpled.

C. L. Liu

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2003

Noise-aware interconnect power optimization in domino logic synthesis.

Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang

IEEE Trans. Very Large Scale Integr. Syst., 2003

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique.

Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang

IEEE Trans. Very Large Scale Integr. Syst., 2003

Compacting sequences with invariant transition frequencies.

Ali Pinar, C. L. Liu

ACM Trans. Design Autom. Electr. Syst., 2003

2002

Synthesis and Optimization of Combinational Interface Circuits.

Ki-Seok Chung, Rajesh K. Gupta, Taewhan Kim, C. L. Liu

J. VLSI Signal Process., 2002

Logic transformation for low-power synthesis.

Ki-Wook Kim, Taewhan Kim, TingTing Hwang, Sung-Mo Kang, C. L. Liu

ACM Trans. Design Autom. Electr. Syst., 2002

Domino logic synthesis based on implication graph.

Ki-Wook Kim, Taewhan Kim, C. L. Liu, Sung-Mo Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A Complete Model for Glitch Analysis in Logic Circuits.

Ki-Seok Chung, Taewhan Kim, C. L. Liu

J. Circuits Syst. Comput., 2002

A technology mapping algorithm for CPLD architectures.

Shih-Liang Chen, TingTing Hwang, C. L. Liu

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Modularized low temperature LNO/PZT/LNO ferroelectric capacitor-over-interconnect (COI) FeRAM for advanced SOC (ASOC) application.

S. L. Lung, Dennis Lin, S. S. Chen, Gary Weng, C. L. Liu, S. C. Lai, C. W. Tsai, T. B. Wu, Rich Liu

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001

G-vector: A New Model for Glitch Analysis in Logic Circuits.

Ki-Seok Chung, Taewhan Kim, C. L. Liu

J. VLSI Signal Process., 2001

Architecture driven circuit partitioning.

Chau-Shen Chen, TingTing Hwang, C. L. Liu

IEEE Trans. Very Large Scale Integr. Syst., 2001

Optimization of the maximum delay of global interconnects duringlayer assignment.

Prashant Saxena, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Binary decision diagram with minimum expected path length.

Yi-Yu Liu, Kuo-Hua Wang, TingTing Hwang, C. L. Liu

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique.

Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang

Proceedings of the 38th Design Automation Conference, 2001

2000

An Integrated Approach to Data Path Synthesis for Behavioral-level Power Optimization.

Chaeryung Park, Taewhan Kim, C. L. Liu

VLSI Design, 2000

A postprocessing algorithm for crosstalk-driven wire perturbation.

Prashant Saxena, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Noise-aware power optimization for on-chip interconnect.

Ki-Wook Kim, Seong-Ook Jung, Unni Narayanan, C. L. Liu, Sung-Mo Kang

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design.

Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

A fine-grained arithmetic optimization technique for high-performance/low-power data path synthesis.

Junhyung Um, Taewhan Kim, C. L. Liu

Proceedings of the 37th Conference on Design Automation, 2000

1999

Partial Scan with Preselected Scan Signals.

Peichen Pan, C. L. Liu

IEEE Trans. Computers, 1999

The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches.

Prashant Saxena, Peichen Pan, C. L. Liu

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

From Time Sharing to Real Time-Sharing of a Really Good Time in the Last 40 Years.

C. L. Liu

Proceedings of the 20th IEEE Real-Time Systems Symposium, 1999

An efficient data path synthesis algorithm for behavioral-level power optimization.

Chaeryung Park, Taewhan Park, C. L. Liu

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Optimal allocation of carry-save-adders in arithmetic optimization.

Junhyung Um, Taewhan Kim, C. L. Liu

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Implication graph based domino logic synthesis.

Ki-Wook Kim, C. L. Liu, Sung-Mo Kang

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Logic Transformation for Low Power Synthesis.

Ki-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu

Proceedings of the 1999 Design, 1999

Crosstalk Minimization Using Wire Perturbations.

Prashant Saxena, C. L. Liu

Proceedings of the 36th Conference on Design Automation, 1999

1998

Register Allocation - A Hierarchical Reduction Approach.

Chaeryung Park, Taewhan Kim, C. L. Liu

J. VLSI Signal Process., 1998

Optimal clock period FPGA technology mapping for sequential circuits.

Peichen Pan, C. L. Liu

ACM Trans. Design Autom. Electr. Syst., 1998

Optimal clock period clustering for sequential circuits with retiming.

Peichen Pan, Arvind K. Karandikar, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Low power logic synthesis under a general delay model.

Unni Narayanan, Peichen Pan, C. L. Liu

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Local transformation techniques for multi-level logiccircuits utilizing circuit symmetries for power reduction.

Ki-Seok Chung, C. L. Liu

Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

A performance-driven layer assignment algorithm for multiple interconnect trees.

Prashant Saxena, C. L. Liu

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Power invariant vector sequence compaction.

Ali Pinar, C. L. Liu

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997

Routing for symmetric FPGAs and FPICs.

Yachyang Sun, Ting-Chi Wang, Chak-Kuen Wong, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Timing-driven placement for regular architectures.

Anmol Mathur, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Optimal Graph Constraint Reduction for Symbolic Layout Compaction.

Peichen Pan, Sai-keung Dong, C. L. Liu

Algorithmica, 1997

Low power logic synthesis for XOR based circuits.

Unni Narayanan, C. L. Liu

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Low Power FPGA Design - A Re-engineering Approach.

Chau-Shen Chen, TingTing Hwang, C. L. Liu

Proceedings of the 34st Conference on Design Automation, 1997

1996

An integrated algorithm for incremental data path synthesis.

Taewhan Kim, C. L. Liu

J. VLSI Signal Process., 1996

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation.

Srilata Raman, C. L. Liu, Larry G. Jones

VLSI Design, 1996

Low power realization of finite state machines - a decomposition approach.

Sue-Hong Chow, Yi-Cheng Ho, TingTing Hwang, C. L. Liu

ACM Trans. Design Autom. Electr. Syst., 1996

Minimum crosstalk channel routing.

Tong Gao, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Area Minimization for Hierarchical Floorplans.

Peichen Pan, Weiping Shi, C. L. Liu

Algorithmica, 1996

An algorithm for synthesis of system-level interface circuits.

Ki-Seok Chung, Rajesh K. Gupta, C. L. Liu

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Technology Mapping of Sequential Circuits for LUT-Based FPGAs for Performance.

Peichen Pan, C. L. Liu

Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs.

Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu

Proceedings of the Euro-Par '96 Parallel Processing, 1996

A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs.

Srilata Raman, C. L. Liu, Larry G. Jones

Proceedings of the 1996 European Design and Test Conference, 1996

Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs.

Anmol Mathur, C. L. Liu

Proceedings of the 1996 European Design and Test Conference, 1996

Desensitization for Power Reduction in Sequential Circuits.

Xiangfeng Chen, Peichen Pan, C. L. Liu

Proceedings of the 33st Conference on Design Automation, 1996

1995

Optimal Reconfiguration Algorithms for Real-Time Fault-Tolerant Processor Arrays.

Ran Libeskind-Hadas, Nimish Shrivastava, Rami G. Melhem, C. L. Liu

IEEE Trans. Parallel Distributed Syst., 1995

Area minimization for floorplans.

Peichen Pan, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

A new approach to the multiport memory allocation problem in data path synthesis.

Taewhan Kim, C. L. Liu

Integr., 1995

Minimum crosstalk switchbox routing.

Tong Gao, C. L. Liu

Integr., 1995

Re-engineering of timing constrained placements for regular architectures.

Anmol Mathur, Kuang-Chien Chen, C. L. Liu

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Applications of Slack Neighborhood Graphs to Timing Driven Optimization Problems in FPGAs.

Anmol Mathur, Kuang-Chien Chen, C. L. Liu

Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays, 1995

Partial Scan with Pre-selected Scan Signals.

Peichen Pan, C. L. Liu

Proceedings of the 32st Conference on Design Automation, 1995

1994

A scheduling algorithm for conditional resource sharing-a hierarchical reduction approach.

Taewhan Kim, Noritake Yonezawa, Jane W.-S. Liu, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Compression-relaxation: a new approach to performance driven placement for regular architectures.

Anmol Mathur, C. L. Liu

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

A delay driven FPGA placement algorithm.

Srilata Raman, C. L. Liu, Larry G. Jones

Proceedings of the Proceedings EURO-DAC'94, 1994

Routing in a New 2-Dimensional FPGA/FPIC Routing Architecture.

Yachyang Sun, C. L. Liu

Proceedings of the 31st Conference on Design Automation, 1994

1993

Modified Rate-Monotonic Algorithm for Scheduling Periodic Jobs with Deferred Deadlines.

Wei-Kuan Shih, Jane W.-S. Liu, C. L. Liu

IEEE Trans. Software Eng., 1993

Physical models and efficient algorithms for over-the-cell routing in standard cell design.

Jason Cong, Bryan Preas, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Register allocation for data flow graphs with conditional branches and loops.

Chaeryung Park, Taewhan Kim, C. L. Liu

Proceedings of the European Design Automation Conference 1993, 1993

A performance driven hierarchical partitioning placement algorithm.

Tong Gao, Chung Laung (Dave) Liu, Kuang-Chien Chen

Proceedings of the European Design Automation Conference 1993, 1993

Utilization of Multiport Memories in Data Path Synthesis.

Taewhan Kim, C. L. Liu

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Fundamentals of Real-Time Scheduling (Extended Abstract).

C. L. Liu

Proceedings of the Real Time Computing, 1992

An Area Minimizer for Floorplans with L-Shaped Regions.

Yachyang Sun, C. L. Liu

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

Area minimization for general floorplans.

Peichen Pan, C. L. Liu

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

A Performance Driven Macro-Cell Placement Algorithm.

Tong Gao, Pravin M. Vaidya, C. L. Liu

Proceedings of the 29th Design Automation Conference, 1992

1991

On the k-layer planar subset and topological via minimization problems.

Jason Cong, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Disjoint Covers in Replicated Heterogeneous Arrays.

Philip K. McKinley, Nany Hasan, Ran Libeskind-Hadas, C. L. Liu

SIAM J. Discret. Math., 1991

Minimum fault covering in reconfigurable arrays.

Nany Hasan, C. L. Liu

Integr., 1991

A Channel Router for Single Layer Customization Technology.

Yachyang Sun, Sai-keung Dong, Shinji Sato, C. L. Liu

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A Scheduling Algorithm for Conditional Resource Sharing.

Taewhan Kim, Jane W.-S. Liu, C. L. Liu

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

A New Performance Driven Placement Algorithm.

Tong Gao, Pravo M. Vaidya, C. L. Liu

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990

Over-the-cell channel routing.

Jason Cong, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

PLA logic minimization by simulated annealing.

Xianjin Yao, C. L. Liu

Integr., 1990

Fault covers in reconfigurable PLAs.

Nany Hasan, C. L. Liu

Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990

Solution of a module orientation and rotation problem.

Xianjin Yao, C. L. Liu

Proceedings of the European Design Automation Conference, 1990

On the k-layer planar subset and via minimization problems.

Jason Cong, C. L. Liu

Proceedings of the European Design Automation Conference, 1990

General Models and Algorithms for Over-the-Cell Routing in Standard Cell Design.

Jason Cong, Bryan Preas, C. L. Liu

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

A new approach to the pin assignment problem.

Xianjin Yao, Masaaki Yamada, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

An enhanced bottom-up algorithm for floorplan design.

Thomas R. Mueller, D. F. Wong, C. L. Liu

Integr., 1989

Generalized latin squares I.

Xiaojun Shen, Y. Z. Cai, C. L. Liu, Clyde P. Kruskal

Discret. Appl. Math., 1989

Floorplan Design of VLSI Circuits.

D. F. Wong, C. L. Liu

Algorithmica, 1989

Constrained floorplan design for flexible blocks.

Sai-keung Dong, Jason Cong, C. L. Liu

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

Solutions to the Module Orientation and Rotation Problems by Neural Computation Networks.

Ran Libeskind-Hadas, C. L. Liu

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

A new approach to three- or four-layer channel routing.

Jason Cong, Martin D. F. Wong, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

A new formulation of yield enhancement problems for reconfigurable chips.

Nany Hasan, Jason Cong, C. L. Liu

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Over-the-cell channel routing.

Jingsheng Cong, C. L. Liu

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Minimum fault coverage in reconfigurable arrays.

Nany Hasan, C. L. Liu

Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

A New Approach to the Pin Assignment Problem.

Xianji Yao, Masaaki Yamada, C. L. Liu

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Algorithms for permutation channel routing.

H. W. Leong, C. L. Liu

Integr., 1987

Array Optimization for VLSI Synthesis.

D. F. Wong, C. L. Liu

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

An Algorithmic Proof of a Generalization of the Birkhoff-Von Neumann Theorem.

James L. Lewandowski, C. L. Liu, Jane W.-S. Liu

J. Algorithms, 1986

Compacted channel routing with via placement restrictions.

D. F. Wong, C. L. Liu

Integr., 1986

A new algorithm for floorplan design.

D. F. Wong, C. L. Liu

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985

Permutation Representation of k-Ary Trees.

Prakash V. Ramanan, C. L. Liu

Theor. Comput. Sci., 1985

1984

Bipartite Folding and Partitioning of a PLA.

Jack R. Egan, C. L. Liu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

A Personnel Assignment Problem.

Prakash V. Ramanan, Jitender S. Deogun, C. L. Liu

J. Algorithms, 1984

A branch and bound algorithm for optimal pla folding.

James L. Lewandowski, C. L. Liu

Proceedings of the 21st Design Automation Conference, 1984

1983

(g 0, g 1, ... g k)-Trees and Unary OL Systems.

D. T. Lee, C. L. Liu, C. K. Wong

Theor. Comput. Sci., 1983

SS/TDMA Time Slot Assignment with Restricted Switching Modes.

James L. Lewandowski, Jane W.-S. Liu, C. L. Liu

IEEE Trans. Commun., 1983

On a Periodic Maintenance Problem.

W.-D. Wei, C. L. Liu

Oper. Res. Lett., 1983

A new channel routing problem.

Hon Wai Leong, C. L. Liu

Proceedings of the 20th Design Automation Conference, 1983

1982

Scheduling with Slack Time.

C. L. Liu, Jane W.-S. Liu, Arthur L. Liestman

Acta Informatica, 1982

Optimal bipartite folding of PLA.

Jack R. Egan, C. L. Liu

Proceedings of the 19th Design Automation Conference, 1982

1980

Generation of trees.

C. L. Liu

Proceedings of the Proc. 5eme Colleque de Lille sur les Arbres en Algebre et en Programmation, 1980

1978

On a Real-Time Scheduling Problem.

Sudarshan K. Dhall, C. L. Liu

Oper. Res., 1978

A generalization of Ramsey theory for graphs.

K. M. Chung, C. L. Liu

Discret. Math., 1978

Performance Analysis of Multiprocessor Systems Containing Functionally Dedicated Processors.

Jane W.-S. Liu, C. L. Liu

Acta Informatica, 1978

1976

Deterministic Job Scheduling in Computing Systems.

C. L. Liu

Proceedings of the Modelling and Performance Evaluation of Computer Systems, 1976

1975

Sperner's theorem on maximal-sized antichains and its generalization.

C. L. Liu

Discret. Math., 1975

1974

On a Class of Scheduling Algorithms for Multiprocessors Computing Systems.

N. F. Chen, C. L. Liu

Proceedings of the Parallel Processing, Proceedings of the Sagamore Computer Conference, 1974

Bounds on Scheduling Algorithms for Heterogeneous Comnputing Systems.

Jane W.-S. Liu, C. L. Liu

Proceedings of the Information Processing, 1974

1973

Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment.

C. L. Liu, James W. Layland

J. ACM, 1973

A construction scheme for linear and non-linear codes.

C. L. Liu, B. G. Ong, Gregory R. Ruth

Discret. Math., 1973

A drum scheduling algorithm.

C. K. Wong, C. L. Liu, J. Apter

Proceedings of the 1. Fachtagung über Automatentheorie und Formale Sprachen, 1973

Analysis of sorting algorithms.

C. L. Liu

Proceedings of the American Federation of Information Processing Societies: 1973 National Computer Conference, 1973

1972

Complementary sets of sequences.

Chin-Chong Tseng, C. L. Liu

IEEE Trans. Inf. Theory, 1972

Analysis and Synthesis of Sorting Algorithms.

C. L. Liu

SIAM J. Comput., 1972

Optimal Scheduling on Multi-Processor Computing Systems

C. L. Liu

Proceedings of the 13th Annual Symposium on Switching and Automata Theory, 1972

1969

A Note on Definite Stochastic Sequential Machines

C. L. Liu

Inf. Control., April, 1969

Lattice Functions, Pair Algebras, and Finite-State Machines.

C. L. Liu

J. ACM, 1969

1967

The design and implementation of a table driven compiler system.

C. L. Liu, G. D. Chang, R. E. Marks

Proceedings of the American Federation of Information Processing Societies: Proceedings of the AFIPS '67 Spring Joint Computer Conference, 1967

1966

Some algebraic properties of multi-threshold functions.

C. L. Liu

IEEE Trans. Electron. Comput., 1966

Pair Algebra and Its Application

C. L. Liu

Proceedings of the 7th Annual Symposium on Switching and Automata Theory, 1966

1964

kth-Order Finite Automaton.

C. L. Liu

IEEE Trans. Electron. Comput., 1964

Sequential-machine realization using feedback shift registers

C. L. Liu

Proceedings of the 5th Annual Symposium on Switching Circuit Theory and Logical Design, 1964