Byungin Moon

Orcid: 0000-0002-8102-4818

According to our database1, Byungin Moon authored at least 23 papers between 2009 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Hardware-friendly architecture for a pseudo 2D weighted median filter based on sparse-window approach.
Multim. Tools Appl., 2021

A Haar Classifier Accelerator with Reduced Multiplexer Usage.
Proceedings of the 18th International SoC Design Conference, 2021

Haar Filter Hardware Architecture for the Accuracy Improvement of Stereo Vision Systems.
Proceedings of the 18th International SoC Design Conference, 2021

Hardware Architecture of a Haar Classifier Based Face Detection System Using a Skip Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Low-cost Hardware Architecture for Integral Image Generation using Word Length Reduction.
Proceedings of the International SoC Design Conference, 2020

2019
Cache memory organization for processing in memory.
IEICE Electron. Express, 2019

2018
Modified adaptive support weight and disparity search range estimation schemes for stereo matching processors.
J. Supercomput., 2018

3D die-stacked DRAM thermal management via task allocation and core pipeline control.
IEICE Electron. Express, 2018

Drivable Area Detection Method Capable of Distinguishing Vegetation Area on Country Road.
Proceedings of the International SoC Design Conference, 2018

2017
The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.
Sensors, 2017

A study of partitioned DIMM tree management for multimedia server systems.
Multim. Tools Appl., 2017

A simplified rectification method and its hardware architecture for embedded multimedia systems.
Multim. Tools Appl., 2017

An accurate and cost-effective stereo matching algorithm and processor for real-time embedded multimedia systems.
Multim. Tools Appl., 2017

An Improved Stereo Matching Algorithm with Robustness to Noise Based on Adaptive Support Weight.
J. Inf. Process. Syst., 2017

A Multi-Level Accumulation-Based Rectification Method and Its Circuit Implementation.
KSII Trans. Internet Inf. Syst., 2017

2015
A census-based stereo matching algorithm with multiple sparse windows.
Proceedings of the Seventh International Conference on Ubiquitous and Future Networks, 2015

2013
Design and analysis of 3D IC-based low power stereo matching processors.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2011
A Rectification Hardware Architecture for an Adaptive Multiple-Baseline Stereo Vision System.
Proceedings of the Communication and Networking, 2011

Hardware Architecture of Bilateral Filter to Remove Haze.
Proceedings of the Communication and Networking, 2011

A Platform for Real Time Brain-Waves Analysis System.
Proceedings of the Grid and Distributed Computing, 2011

An Efficient Interworking Architecture of a Network Processor for Layer 7 Packet Processing.
Proceedings of the Communication and Networking, 2011

2010
A Fully Parallel, High-Speed BPC Hardware Architecture for the EBCOT in JPEG 2000.
Proceedings of the Communication and Networking, 2010

2009
Efficient Data Transmission Scheme among Multi-devices.
Proceedings of the Communication and Networking, 2009


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