Byung-Sik Moon

According to our database¹, Byung-Sik Moon authored at least 4 papers between 1996 and 1999.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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Bibliography

1999

A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1999

1998

A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1998

1997

Low-voltage, high-speed circuit designs for gigabit DRAMs.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1997

1996

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1996

Byung-Sik Moon

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Bibliography

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