Byung-Kwon An

According to our database, Byung-Kwon An authored at least 4 papers between 2023 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A 1-Mb RRAM Macro With 9.8 ns Read Access Time Utilizing Dynamic Reference Voltage for Reliable Sensing Operation.

Junjie Mu, Lu Lu, Ju Eon Kim, Byung-Kwon An, Vishal Sharma, Arya Jagath Lekshmi, Putu Andhita Dananjaya, Weng Hong Lai, Wen Siang Lew, Tony Tae-Hyoung Kim

IEEE Trans. Circuits Syst. II Express Briefs, May, 2024

Time-based Sensing with Linear Current-to-Time Conversion for Multi-level Resistive Memory.

Byung-Kwon An, Xueyong Zhang, Anh Tuan Do, Tony Tae-Hyoung Kim

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2023

A Robust Time-Based Multi-Level Sensing Circuit for Resistive Memory.

Xueyong Zhang, Byung-Kwon An, Tony Tae-Hyoung Kim

IEEE Trans. Circuits Syst. I Regul. Pap., January, 2023

Design of a Current Sense Amplifier with Dynamic Reference for Reliable Resistive Memory.

Byung-Kwon An, Xueyong Zhang, Anh Tuan Do, Tony Tae-Hyoung Kim

Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023