Byung-Kwan Chun
According to our database1,
Byung-Kwan Chun
authored at least 9 papers
between 2007 and 2024.
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Collaborative distances:
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2024
13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 3.0 Gb/s/pin 4<sup>th</sup> generation F-chip with Toggle 5.0 Specification for 16Tb NAND Flash Memory Multi chip Package.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2021
A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage.
IEEE J. Solid State Circuits, 2021
A Hybrid ZQ Calibration Design for High-Density Flash Memory Toggle 5.0 High-speed Interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2014
IEEE Trans. Commun., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
2011
A Synthesis-Based Bandwidth Enhancement Technique for CMOS Amplifiers: Theory and Design.
IEEE J. Solid State Circuits, 2011
2007
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007