Byung-Hun Min

According to our database, Byung-Hun Min authored at least 3 papers between 2011 and 2013.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2013

1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector.

Sangjin Byun, Chung Hwan Son, Jongil Hwang, Byung-Hun Min, Mun-Yang Park, Hyun-Kyu Yu

IET Circuits Devices Syst., 2013

2012

A 4-GHz All Digital PLL With Low-Power TDC and Phase-Error Compensation.

Ja-Yol Lee, Mi-Jeong Park, Byung-Hun Min, Seongdo Kim, Mun-Yang Park, Hyun-Kyu Yu

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

2011

A low power discrete-time receiver for triple-band FM/T-DMB/DAB system-on-chip.

Hoai-Nam Nguyen, Seung-Hwan Jung, Byung-Hun Min, Young-Jae Lee, Sang-Gug Lee, Yun Seong Eo, Hyun-Kyu Yu

Proceedings of the 37th European Solid-State Circuits Conference, 2011