Byung-Do Yang

Sensors, October, 2023

2020

A 0.35V 90nA Quiescent Current Output-Capacitor-Less NMOS Low-Dropout Regulator Using a Coarse-Fine Charge-Pump Circuit.

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[DOI]

IEEE Trans. Circuits Syst., 2020

A 0.25-V Rail-to-Rail Three-Stage OTA With an Enhanced DC Gain.

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[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

0.3-V RC-to-Digital Converter Using a Negative Charge-Pump Switch.

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[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Low-Area and Low-Power Latch-Based Thermometer-Code Shift-Register.

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[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering.

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[DOI]

IEEE Access, 2020

2019

DC-DC Buck Converter Using Analog Coarse-Fine Self-Tracking Zero-Current Detection Scheme.

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[DOI]

Jae-Mun Oh

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Area-Efficient Bidirectional Shift-Register Using Bidirectional Pulsed-Latches.

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[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2019

Depth Map Estimation Model with Efficient Feature Extraction Module.

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[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2019

A Voltage-Mode Buck Converter With a Reduced Type-I Compensation Capacitor Using an Error-Amplifier Current-Sampling Scheme.

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[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2019

Low Power Digital PWM Buck Converter With a Clock-Gating Shift-Register.

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[DOI]

Proceedings of the International Conference on Electronics, Information, and Communication, 2019

2018

Low-Area TCAM Using A Don't Care Reduction Scheme.

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[DOI]

IEEE J. Solid State Circuits, 2018

2017

Extracting the Source Code Context to Predict Import Changes using GPES.

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[DOI]

KSII Trans. Internet Inf. Syst., 2017

2015

Low-Power and Area-Efficient Shift Register Using Pulsed Latches.

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[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Low-Power Effective Memory-Size Expanded TCAM Using Data-Relocation Scheme.

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[DOI]

IEEE J. Solid State Circuits, 2015

2014

250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit.

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[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

2012

Low-Power Time Deinterleaver for ISDB-T Receiver.

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[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2012

2011

A Low Power Content Addressable Memory Using Low Swing Search Lines.

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[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Area-Efficient Prefilter Architecture for a CDMA Receiver.

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[DOI]

Seung Jae Lee

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A High-Efficiency On-Chip DC-DC Down-Conversion Using Selectable Supply-Voltage Charge-Recycling.

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[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010

A Low-Power SRAM Using Bit-Line Charge-Recycling for Read and Write Operations.

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[DOI]

IEEE J. Solid State Circuits, 2010

2009

A Fast-switching Current-pulse Driver for LED Backlight.

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[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

A highly accurate BiCMOS cascode current mirror for wide output voltage range.

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[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme.

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[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

A low-power ROM using single charge-sharing capacitor and hierarchical bit line.

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[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

2005

A low-power CAM using pulsed NAND-NOR match-line and charge-recycling search-line driver.

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[DOI]

IEEE J. Solid State Circuits, 2005

A low-power SRAM using hierarchical bit line and local sense amplifiers.

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[DOI]

IEEE J. Solid State Circuits, 2005

2004

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter.

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[DOI]

IEEE J. Solid State Circuits, 2004

An error pattern ROM compression method for continuous data.

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Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

A low-power charge-recycling ROM architecture.

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[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

A low-power ROM using charge recycling and charge sharing techniques.

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[DOI]

IEEE J. Solid State Circuits, 2003

A low power charge sharing ROM using dummy bit lines.

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[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

A high speed direct digital frequency synthesizer using a low power pipelined parallel accumulator.

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[DOI]

Hyun-Kyu Yu

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A ROM compression method for continuous data.

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[DOI]