Byoung-Mo Moon

According to our database1, Byoung-Mo Moon authored at least 8 papers between 2008 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s.
IEEE J. Solid State Circuits, November, 2023

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022
A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC.
IEEE J. Solid State Circuits, 2022

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface With V<sub>OH</sub> Drift Control.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 6.9-μm<sup>2</sup> 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme.
IEEE J. Solid State Circuits, 2021

2008
Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation.
IEEE Trans. Circuits Syst. II Express Briefs, 2008


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