Byeong-Gyu Nam
Orcid: 0000-0003-0069-1959
According to our database1,
Byeong-Gyu Nam
authored at least 29 papers
between 2005 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
2006
2008
2010
2012
2014
2016
2018
2020
2022
2024
0
1
2
3
4
5
6
2
1
1
1
2
1
1
2
1
1
1
2
3
1
1
1
1
1
4
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Enhancing Computation-Efficiency of Deep Neural Network Processing on Edge Devices through Serial/Parallel Systolic Computing.
Mach. Learn. Knowl. Extr., September, 2024
IEEE Access, 2024
2021
IEEE Access, 2021
2020
IEEE Trans. Circuits Syst., 2020
2018
Session 13 overview: Machine learning and signal processing: Digital architectures and systems subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A self-powered always-on vision-based wake-up detector for wearable gesture user interfaces.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A low-power real-time hidden Markov model accelerator for gesture user interface on wearable devices.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A 27 mW Reconfigurable Marker-Less Logarithmic Camera Pose Estimation Engine for Mobile Augmented Reality Processor.
IEEE J. Solid State Circuits, 2015
2014
Intelligent Network-on-Chip With Online Reinforcement Learning for Portable HD Object Recognition Processor.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE J. Solid State Circuits, 2014
A 27mW reconfigurable marker-less logarithmic camera pose estimation engine for mobile augmented reality processor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A 57 mW 12.5 µJ/Epoch Embedded Mixed-Mode Neuro-Fuzzy Processor for Mobile Real-Time Object Recognition.
IEEE J. Solid State Circuits, 2013
A high-throughput 16× super resolution processor for real-time object recognition SoC.
Proceedings of the ESSCIRC 2013, 2013
2012
Session 12 overview: Multimedia and communications SoCs: Energy-efficient digital subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2009
An Embedded Stream Processor Core Based on Logarithmic Arithmetic for a Low-Power 3-D Graphics SoC.
IEEE J. Solid State Circuits, 2009
2008
Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems.
IEEE Trans. Computers, 2008
IEEE Commun. Mag., 2008
2007
IEEE J. Solid State Circuits, 2007
A 52.4mW 3D Graphics Processor with 141Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency Scaling.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for Dynamic Voltage and Frequency Scaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
A low-power vector processor using logarithmic arithmetic for handheld 3d graphics systems.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
Proceedings of the ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware 2007, 2007
2006
A 231-MHz, 2.18-mW 32-bit Logarithmic Arithmetic Unit for Fixed-Point 3-D Graphics System.
IEEE J. Solid State Circuits, 2006
2005
Development of a 3-D graphics rendering engine with lighting acceleration for handheld multimedia systems.
IEEE Trans. Consumer Electron., 2005
A fixed-point 3D graphics library with energy-efficient cache architecture for mobile multimedia systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005