Bulent I. Dervisoglu

According to our database, Bulent I. Dervisoglu authored at least 20 papers between 1973 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2002

Reducing Time to Volume and Time to Market: Is Silicon Debug and Diagnosis the Answer?

Fidel Muradali, Mike Ricchetti, Bart Vermeulen, Bulent I. Dervisoglu, Bob Gottlieb, Bernd Koenemann, C. J. Clark

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

2001

A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers.

Bulent I. Dervisoglu

Proceedings of the 38th Design Automation Conference, 2001

1999

Design for testability: it is time to deliver it for Time-to-Market.

Bulent I. Dervisoglu

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998

Shared I/O-cell structures: a framework for extending the IEEE 1149.1 boundary-scan standard.

Bulent I. Dervisoglu, Mike Ricchetti, William Eklow

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1995

Special Report: Shared-I/O Scan Test.

Bulent I. Dervisoglu

IEEE Des. Test Comput., 1995

1994

Microprocessor Testing: Which Technique is Best? (Panel).

Jacob A. Abraham, Sandip Kundu, Janak H. Patel, Manuel A. d'Abreu, Bulent I. Dervisoglu, Marc E. Levitt, Hector R. Sucar, Ron G. Walther

Proceedings of the 31st Conference on Design Automation, 1994

1992

Boundary-Scan Update: IEEE P1149.2 Description and Status Report.

Bulent I. Dervisoglu

IEEE Des. Test Comput., 1992

1991

Features of a Scan and Clock Resource chip for providing access to board-level test functions.

Bulent I. Dervisoglu

J. Electron. Test., 1991

Application of Scan-Based DFT Methodology for Detecting Static and Timing Failures in VLSI Components.

Bulent I. Dervisoglu, Gayvin E. Stong

Proceedings of the VLSI 91, 1991

Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement.

Bulent I. Dervisoglu, Gayvin E. Stong

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

Application of scan hardware and software for debug and diagnostics in a workstation environment.

Bulent I. Dervisoglu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Towards a standard approach for controlling board-level test functions.

Bulent I. Dervisoglu

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989

Scan-path architecture for pseudorandom testing.

Bulent I. Dervisoglu

IEEE Des. Test, 1989

ATLAS/ELA: Scan-based Software Tools for Reducing System Debug Time in a State-of-the-art Workstation.

Bulent I. Dervisoglu, M. A. Keil

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Using Scan Technology for Debug and Diagnostics in a Workstation Environment.

Bulent I. Dervisoglu

Proceedings of the Proceedings International Test Conference 1988, 1988

1984

On Coosing a Hardware Descriptive Language for Digital Systems Testing/Verification.

Bulent I. Dervisoglu

Proceedings of the Proceedings International Test Conference 1984, 1984

1981

A Hard Progammable Control Unit Design Using VLSI Technology.

Bulent I. Dervisoglu, Donald J. Criscione

IEEE Trans. Computers, 1981

1980

Theory and Design of Mixed-Mode Sequential Machines.

Bulent I. Dervisoglu, Howard A. Sholl

IEEE Trans. Computers, 1980

1974

Hardware description languages in Great Britain.

Bulent I. Dervisoglu

Computer, 1974

1973

Computer aided design techniques applied to logic design.

Bulent I. Dervisoglu

PhD thesis, 1973