Bülent Abali

According to our database1, Bülent Abali authored at least 44 papers between 1993 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Enterprise-Class Cache Compression Design.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2021
EFloat: Entropy-coded Floating Point Format for Deep Learning.
CoRR, 2021

2020
Design and verification of DEFLATE acceleration as an architected instruction in z15.
IBM J. Res. Dev., 2020

Data Compression Accelerator on IBM POWER9 and z15 Processors : Industrial Product.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

2019
Touché: Towards Ideal and Efficient Cache Compression By Mitigating Tag Area Overheads.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018
IBM POWER9 processor and system features for computing in the cognitive era.
IBM J. Res. Dev., 2018

Towards a Single-Host Many-GPU System.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

Attaché: Towards Ideal Memory Compression by Mitigating Metadata Bandwidth Overheads.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Towards a Composable Computer System.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2018

2017
Composable architecture for rack scale big data computing.
Future Gener. Comput. Syst., 2017

2015
Disaggregated and optically interconnected memory: when will it be cost effective?
CoRR, 2015

2013
IBM POWER7+ processor on-chip accelerators for cryptography and active memory expansion.
IBM J. Res. Dev., 2013

2012
Eucalyptus: Support for Effective Use of Persistent Memory.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

2011
Improving server utilization using fast virtual machine migration.
IBM J. Res. Dev., 2011

High-Throughput, Lossless Data Compresion on FPGAs.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

2009
Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Evaluating high performance communication: a power perspective.
Proceedings of the 23rd international conference on Supercomputing, 2009

Virtualization polling engine (VPE): using dedicated CPU cores to accelerate I/O virtualization.
Proceedings of the 23rd international conference on Supercomputing, 2009

2008
Flipstone: managing storage with fail-in-place and deferred maintenance service models.
ACM SIGOPS Oper. Syst. Rev., 2008

PAM: a novel performance/power aware meta-scheduler for multi-core systems.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

Sysman: A Virtual File System for Managing Clusters.
Proceedings of the 22nd Large Installation System Administration Conference, 2008

2007
Nomad: migrating OS-bypass networks in virtual machines.
Proceedings of the 3rd International Conference on Virtual Execution Environments, 2007

2006
High Performance VMM-Bypass I/O in Virtual Machines.
Proceedings of the 2006 USENIX Annual Technical Conference, 2006

A case for high performance computing with virtual machines.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006

2005
Storage-based file system integrity checker.
Proceedings of the 2005 ACM Workshop On Storage Security And Survivability, 2005

Storage-Based Intrusion Detection for Storage Area Networks (SANs).
Proceedings of the 22nd IEEE / 13th NASA Goddard Conference on Mass Storage Systems and Technologies (MSST 2005), 2005

2001
Hardware Compressed Main Memory: Operating System Support and Performance Evaluation.
IEEE Trans. Computers, 2001

Design Alternatives for Virtual Interface Architecture and an Implementation on IBM Netfinity NT Cluster.
J. Parallel Distributed Comput., 2001

Adaptive Routing on the New Switch Chip for IBM SP Systems.
J. Parallel Distributed Comput., 2001

Memory Expansion Technology (MXT): Competitive impact.
IBM J. Res. Dev., 2001

Memory Expansion Technology (MXT): Software support and performance.
IBM J. Res. Dev., 2001

Performance of Hardware Compressed Main Memory.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000
Adaptive Routing in RS/6000 SP-Like Bidirectional Multistage Interconnection Networks.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Efficient Virtual Interface Architecture (VIA) Support for the IBM SP Switch-Connected NT Clusters.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Comparison and Evaluation of Design Choices for Implementing the Virtual Interface Architecture (VIA).
Proceedings of the Network-Based Parallel Computing: Communication, 2000

1999
A New Switch Chip for IBM RS/6000 SP Systems.
Proceedings of the ACM/IEEE Conference on Supercomputing, 1999

1997
Clock Synchronization on a Multicomputer.
J. Parallel Distributed Comput., 1997

A Deadlock Avoidance Method for Computer Networks.
Proceedings of the Communication and Architectural Support for Network-Based Parallel Computing, 1997

1996
Adaptive Source Routing in Multistage Interconnection Networks.
Proceedings of IPPS '96, 1996

1995
The SP2 High-Performance Switch.
IBM Syst. J., 1995

Time synchronization on SP1 and SP2 parallel systems.
Proceedings of IPPS '95, 1995

1994
Routing Algorithms for IBM SP1.
Proceedings of the Parallel Computer Routing and Communication, 1994

Architecture and Implementation of Vulcan.
Proceedings of the 8th International Symposium on Parallel Processing, 1994

1993
Balanced Parallel Sort on Hypercube Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 1993


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