Bucknell C. Webb

According to our database, Bucknell C. Webb authored at least 7 papers between 2005 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2013

A 2.5D Integrated Voltage Regulator Using Coupled-Magnetic-Core Inductors on Silicon Interposer.

Noah Sturcken, Eugene J. O'Sullivan, Naigang Wang, Philipp Herget, Bucknell C. Webb, Lubomyr T. Romankiw, Michele Petracca, Ryan Davies, Robert E. Fontana Jr., Gary M. Decad, Ioannis Kymissis, Angel V. Peterchev, Luca P. Carloni, William J. Gallagher, Kenneth L. Shepard

IEEE J. Solid State Circuits, 2013

2012

A 2.5D integrated voltage regulator using coupled-magnetic-core inductors on silicon interposer delivering 10.8A/mm².

Noah Sturcken, Eugene J. O'Sullivan, Naigang Wang, Philipp Herget, Bucknell C. Webb, Lubomyr T. Romankiw, Michele Petracca, Ryan Davies, Robert E. Fontana Jr., Gary M. Decad, Ioannis Kymissis, Angel V. Peterchev, Luca P. Carloni, William J. Gallagher, Kenneth L. Shepard

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2008

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections.

Katsuyuki Sakuma, Paul S. Andry, Cornelia K. Tsang, Steven L. Wright, Bing Dang, Chirag S. Patel, Bucknell C. Webb, J. Maria, Edmund J. Sprogis, S. K. Kang, Robert J. Polastre, Raymond R. Horton, John U. Knickerbocker

IBM J. Res. Dev., 2008

Three-dimensional silicon integration.

John U. Knickerbocker, Paul S. Andry, Bing Dang, Raymond R. Horton, Mario J. Interrante, Chirag S. Patel, Robert J. Polastre, Katsuyuki Sakuma, Ranjani Sirdeshmukh, Edmund J. Sprogis, Sri M. Sri-Jayantha, Antonio M. Stephens, Anna W. Topol, Cornelia K. Tsang, Bucknell C. Webb, Steven L. Wright

IBM J. Res. Dev., 2008

3D chip stacking with C4 technology.

Bing Dang, Steven L. Wright, Paul S. Andry, Edmund J. Sprogis, Cornelia K. Tsang, M. John Interrante, Bucknell C. Webb, Robert J. Polastre, Raymond R. Horton, Chirag S. Patel, Arun Sharma, J. Zheng, Katsuyuki Sakuma, John U. Knickerbocker

IBM J. Res. Dev., 2008

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications.

Paul S. Andry, Cornelia K. Tsang, Bucknell C. Webb, Edmund J. Sprogis, Steven L. Wright, Bing Dang, Dennis G. Manzer

IBM J. Res. Dev., 2008

2005

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection.

John U. Knickerbocker, Paul S. Andry, L. Paivikki Buchwalter, Alina Deutsch, Raymond R. Horton, Keith A. Jenkins, Young Hoon Kwark, Gerald McVicker, Chirag S. Patel, Robert J. Polastre, Christian D. Schuster, Arun Sharma, Sri M. Sri-Jayantha, Christopher W. Surovic, Cornelia K. Tsang, Bucknell C. Webb, Steven L. Wright, Samuel R. McKnight, Edmund J. Sprogis, Bing Dang

IBM J. Res. Dev., 2005