Bruno W. Garlepp
According to our database1,
Bruno W. Garlepp
authored at least 13 papers
between 1999 and 2010.
Collaborative distances:
Collaborative distances:
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Bibliography
2010
A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator.
IEEE J. Solid State Circuits, 2010
A low-area switched-resistor loop-filter technique for fractional-N synthesizers applied to a MEMS-based programmable oscillator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2008
A 12-GS/s Phase-Calibrated CMOS Digital-to-Analog Converter for Backplane Communications.
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
2007
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A new technique for characterization of digital-to-analog converters in high-speed systems.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition.
IEEE J. Solid State Circuits, 2006
A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery.
IEEE J. Solid State Circuits, 2005
Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2001
IEEE J. Solid State Circuits, 2001
1999
IEEE J. Solid State Circuits, 1999