Bruno Forlin
Orcid: 0000-0003-4822-1841
According to our database1,
Bruno Forlin
authored at least 18 papers
between 2018 and 2024.
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Bibliography
2024
Design and Experimental Investigation of Trikarenos: A Fault-Tolerant 28nm RISC-V-based SoC.
CoRR, 2024
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024
An Experimental Comparison of RISC-V Processors: Performance, Power, Area and Security - Special Session Paper-.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Integr., 2023
An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds?
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
2022
J. Syst. Archit., 2022
Aggressive Performance Improvement on Processing-in-Memory Devices by Adopting Hugepages.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022
2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the IEEE European Test Symposium, 2020
2019
Security Aspects of Real-Time MPSoCs: The Flaws and Opportunities of Preemptive NoCs.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018