Brucek Khailany

According to our database, Brucek Khailany authored at least 84 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

ESPACE: Dimensionality Reduction of Activations for Model Compression.

Charbel Sakr, Brucek Khailany

CoRR, 2024

Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks.

Nathaniel Ross Pinckney, Christopher Batten, Mingjie Liu, Haoxing Ren, Brucek Khailany

CoRR, 2024

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool.

Chia-Tung Ho, Haoxing Ren, Brucek Khailany

CoRR, 2024

PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs.

Christopher Batten, Nathaniel Ross Pinckney, Mingjie Liu, Haoxing Ren, Brucek Khailany

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

2023

Machine Learning and Algorithms: Let Us Team Up for EDA.

Haoxing Ren, Brucek Khailany, Matthew Fojtik, Yanqing Zhang

IEEE Des. Test, February, 2023

A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm.

Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany

IEEE J. Solid State Circuits, 2023

ChipNeMo: Domain-Adapted LLMs for Chip Design.

Mingjie Liu, Teodor-Dumitru Ene, Robert Kirby, Chris Cheng, Nathaniel Ross Pinckney, Rongjian Liang, Jonah Alben, Himyanshu Anand, Sanmitra Banerjee, Ismet Bayraktaroglu, Bonita Bhaskaran, Bryan Catanzaro, Arjun Chaudhuri, Sharon Clay, Bill Dally, Laura Dang, Parikshit Deshpande, Siddhanth Dhodhi, Sameer Halepete, Eric Hill, Jiashang Hu, Sumit Jain, Brucek Khailany, Kishor Kunal, Xiaowei Li, Hao Liu, Stuart F. Oberman, Sujeet Omar, Sreedhar Pratty, Jonathan Raiman, Ambar Sarkar, Zhengjiang Shao, Hanfei Sun, Pratik P. Suthar, Varun Tej, Kaizhe Xu, Haoxing Ren

CoRR, 2023

VerilogEval: Evaluating Large Language Models for Verilog Code Generation.

Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren

CoRR, 2023

NVCell 2: Routability-Driven Standard Cell Layout in Advanced Nodes with Lattice Graph Routability Model.

Chia-Tung Ho, Alvin Ho, Matthew Fojtik, Minsoo Kim, Shang Wei, Yaguang Li, Brucek Khailany, Haoxing Ren

Proceedings of the 2023 International Symposium on Physical Design, 2023

AutoDMP: Automated DREAMPlace-based Macro Placement.

Anthony Agnesina, Puranjay Rajvanshi, Tian Yang, Geraldo Pradipta, Austin Jiao, Ben Keller, Brucek Khailany, Haoxing Ren

Proceedings of the 2023 International Symposium on Physical Design, 2023

An Adversarial Active Sampling-Based Data Augmentation Framework for AI-Assisted Lithography Modeling.

Mingjie Liu, Haoyu Yang, Brucek Khailany, Haoxing Ren

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation.

Mingjie Liu, Nathaniel Ross Pinckney, Brucek Khailany, Haoxing Ren

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

GenFuzz: GPU-accelerated Hardware Fuzzing using Genetic Algorithm with Multiple Inputs.

Dian-Lun Lin, Yanqing Zhang, Haoxing Ren, Brucek Khailany, Shih-Hsin Wang, Tsung-Wei Huang

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Late Breaking Results: Test Selection For RTL Coverage By Unsupervised Learning From Fast Functional Simulation.

Rongjian Liang, Nathaniel Ross Pinckney, Yuji Chai, Haoxin Ren, Brucek Khailany

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Efficient Transformer Inference with Statically Structured Sparse Attention.

Steve Dai, Hasan Genc, Rangharajan Venkatesan, Brucek Khailany

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update.

Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Fayez Ali, Ming-Yu Liu, Brucek Khailany, William J. Dally, Anima Anandkumar

IEEE Trans. Computers, 2022

HEAT: Hardware-Efficient Automatic Tensor Decomposition for Transformer Compression.

Jiaqi Gu, Ben Keller, Jean Kossaifi, Anima Anandkumar, Brucek Khailany, David Z. Pan

CoRR, 2022

An Adversarial Active Sampling-based Data Augmentation Framework for Manufacturable Chip Design.

Mingjie Liu, Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Selim Dogru, Anima Anandkumar, David Z. Pan, Brucek Khailany, Haoxing Ren

CoRR, 2022

Large Scale Mask Optimization Via Convolutional Fourier Neural Operator and Litho-Guided Self Training.

Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Anima Anandkumar, Brucek Khailany, Vivek Singh, Haoxing Ren

CoRR, 2022

A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm.

Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning.

Vidya A. Chhabria, Ben Keller, Yanqing Zhang, Sandeep Vollala, Sreedhar Pratty, Haoxing Ren, Brucek Khailany

Proceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD, 2022

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies.

Hao Chen, Walker J. Turner, Sanquan Song, Keren Zhu, George F. Kokai, Brian Zimmer, C. Thomas Gray, Brucek Khailany, David Z. Pan, Haoxing Ren

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch Stimulus.

Dian-Lun Lin, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Tsung-Wei Huang

Proceedings of the 51st International Conference on Parallel Processing, 2022

Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training.

Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany

Proceedings of the International Conference on Machine Learning, 2022

TransSizer: A Novel Transformer-Based Fast Gate Sizer.

Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

GATSPI: GPU accelerated gate-level simulation for power improvement.

Yanqing Zhang, Haoxing Ren, Akshay Sridharan, Brucek Khailany

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Generic lithography modeling with dual-band optics-inspired neural networks.

Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Haoxing Ren

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Generative self-supervised learning for gate sizing: invited.

Siddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

Yibo Lin, Zixuan Jiang, Jiaqi Gu, Wuxi Li, Shounak Dhar, Haoxing Ren, Brucek Khailany, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning.

Haoxing Ren, Matthew Fojtik, Brucek Khailany

CoRR, 2021

Low-Precision Training in Logarithmic Number System using Multiplicative Weight Update.

Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Ming-Yu Liu, Brucek Khailany, Bill Dally, Anima Anandkumar

CoRR, 2021

Verifying High-Level Latency-Insensitive Designs with Formal Model Checking.

Steve Dai, Alicia Klinefelter, Haoxing Ren, Rangharajan Venkatesan, Ben Keller, Nathaniel Ross Pinckney, Brucek Khailany

CoRR, 2021

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference.

Steve Dai, Rangharajan Venkatesan, Haoxing Ren, Brian Zimmer, William J. Dally, Brucek Khailany

CoRR, 2021

Simba: scaling deep-learning inference with chiplet-based architecture.

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler

Commun. ACM, 2021

VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference.

Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William J. Dally, Brucek Khailany

Proceedings of the Fourth Conference on Machine Learning and Systems, 2021

3.2 The A100 Datacenter GPU and Ampere Architecture.

Jack Choquette, Ming-Ju Edward Lee, Ronny Krashinsky, Vishnu Balan, Brucek Khailany

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper.

Haoxing Ren, Saad Godil, Brucek Khailany, Robert Kirby, Haiguang Liao, Siddhartha Nath, Jonathan Raiman, Rajarshi Roy

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

IPA: Floorplan-Aware SystemC Interconnect Performance Modeling and Generation for HLS-based SoCs.

Nathaniel Ross Pinckney, Rangharajan Venkatesan, Ben Keller, Brucek Khailany

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2021 ICCAD CAD Contest Problem C: GPU Accelerated Logic Rewriting.

Ghasem Pasandi, Sreedhar Pratty, David Brown, Yanqing Zhang, Haoxing Ren, Brucek Khailany

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization.

Mingjie Liu, Walker J. Turner, George F. Kokai, Brucek Khailany, David Z. Pan, Haoxing Ren

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification.

Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Softermax: Hardware/Software Co-Design of an Efficient Softmax for Transformers.

Jacob R. Stevens, Rangharajan Venkatesan, Steve Dai, Brucek Khailany, Anand Raghunathan

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

ABCDPlace: Accelerated Batch-Based Concurrent Detailed Placement on Multithreaded CPUs and GPUs.

Yibo Lin, Wuxi Li, Jiaqi Gu, Haoxing Ren, Brucek Khailany, David Z. Pan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Accelerating Chip Design With Machine Learning.

Brucek Khailany, Haoxing Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William J. Dally

IEEE Micro, 2020

A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm.

Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany

IEEE J. Solid State Circuits, 2020

MAVIREC: ML-Aided Vectored IR-DropEstimation and Classification.

Vidya A. Chhabria, Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany, Sachin S. Sapatnekar

CoRR, 2020

Accelerating Chip Design with Machine Learning.

Brucek Khailany

Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk).

Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk).

Yanqing Zhang, Haoxing Ren, Brucek Khailany

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation.

Yanqing Zhang, Haoxing Ren, Brucek Khailany

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network.

Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning.

Zhiyao Xie, Guan-Qi Fang, Yu-Hung Huang, Haoxing Ren, Yanqing Zhang, Brucek Khailany, Shao-Yun Fang, Jiang Hu, Yiran Chen, Erick Carvajal Barboza

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm.

Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture.

Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Timeloop: A Systematic Approach to DNN Accelerator Evaluation.

Angshuman Parashar, Priyanka Raina, Yakun Sophia Shao, Yu-Hsin Chen, Victor A. Ying, Anurag Mukkara, Rangharajan Venkatesan, Brucek Khailany, Stephen W. Keckler, Joel S. Emer

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

MAGNet: A Modular Accelerator Generator for Neural Networks.

Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany

Proceedings of the International Conference on Computer-Aided Design, 2019

A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology.

Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany

Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

PRIMAL: Power Inference using Machine Learning.

Yuan Zhou, Haoxing Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference.

Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

High Performance Graph Convolutional Networks with Applications in Testability Analysis.

Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement.

Yibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.

Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany

Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

2018

Hardware-Enabled Artificial Intelligence.

William J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson, Larry R. Dennison

Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A modular digital VLSI flow for high-productivity SoC design.

Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks.

Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally

Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017

2016

A real-time energy-efficient superpixel hardware accelerator for mobile computer vision applications.

Injoon Hong, Jason Clemons, Rangharajan Venkatesan, Iuri Frosio, Brucek Khailany, Stephen W. Keckler

Proceedings of the 53rd Annual Design Automation Conference, 2016

Modeling and Analysis of Power Supply Noise Tolerance with Fine-Grained GALS Adaptive Clocks.

Divya Akella Kamakshi, Matthew Fojtik, Brucek Khailany, Sudhir S. Kudva, Yaping Zhou, Benton H. Calhoun

Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2015

A Pausible Bisynchronous FIFO for GALS Systems.

Ben Keller, Matthew Fojtik, Brucek Khailany

Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2013

GPU design in a power-limited era.

Brucek Khailany

Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

2012

Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor.

Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally

Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

2011

GPUs and the Future of Parallel Computing.

Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco

IEEE Micro, 2011

CudaDMA: optimizing GPU memory bandwidth via warp specialization.

Michael Bauer, Henry Cook, Brucek Khailany

Proceedings of the Conference on High Performance Computing Networking, 2011

2008

A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing.

Brucek Khailany, Ted Williams, Jim Lin, Eileen Peters Long, Mark Rygh, DeForest Tovey, William J. Dally

IEEE J. Solid State Circuits, 2008

2004

Stream Processors: Progammability and Efficiency.

William J. Dally, Ujval J. Kapasi, Brucek Khailany, Jung Ho Ahn, Abhishek Das

ACM Queue, 2004

Evaluating the Imagine Stream Architecture.

Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das

Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2003

Programmable Stream Processors.

Ujval J. Kapasi, Scott Rixner, William J. Dally, Brucek Khailany, Jung Ho Ahn, Peter R. Mattson, John D. Owens

Computer, 2003

Exploring the VLSI Scalability of Stream Processors.

Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles

Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

2002

VLSI Design and Verification of the Imagine Processor.

Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

The Imagine Stream Processor.

Ujval J. Kapasi, William J. Dally, Scott Rixner, John D. Owens, Brucek Khailany

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Comparing Reyes and OpenGL on a Stream Architecture.

John D. Owens, Brucek Khailany, Brian Towles, William J. Dally

Proceedings of the 2002 ACM SIGGRAPH/EUROGRAPHICS Conference on Graphics Hardware, 2002

2001

Imagine: Media Processing with Streams.

Brucek Khailany, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, John D. Owens, Brian Towles, Andrew Chang, Scott Rixner

IEEE Micro, 2001

2000

Efficient conditional operations for data-parallel architectures.

Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany

Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

Register Organization for Media Processing.

Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens

Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1998

A Bandwidth-efficient Architecture for Media Processing.

Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo López-Lagunas, Peter R. Mattson, John D. Owens

Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998