Bruce Querbach

According to our database, Bruce Querbach authored at least 4 papers between 2013 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC.

Bruce Querbach, Rahul Khanna, Sudeep Puligundla, David Blankenbeckler, Joseph Crop, Patrick Yin Chiang

IEEE Des. Test, 2016

2015

Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine.

Bruce Querbach, Tan Peter Yanyang, Lovelace Van, David Blankenbeckler, Rahul Khanna, Sudeep Puligundla, Patrick Chiang

Proceedings of the 2015 IEEE International Test Conference, 2015

2014

A reusable BIST with software assisted repair technology for improved memory and IO debug, validation and test time.

Bruce Querbach, Rahul Khanna, David Blankenbeckler, Yulan Zhang, Ronald T. Anderson, David G. Ellis, Zale T. Schoenborn, Sabyasachi Deyati, Patrick Chiang

Proceedings of the 2014 International Test Conference, 2014

2013

Comparison of hardware based and software based stress testing of memory IO interface.

Bruce Querbach, Sudeep Puligundla, Daniel Becerra, Zale T. Schoenborn, Patrick Chiang

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013