Bruce M. Fleischer
Orcid: 0000-0002-7033-1564
According to our database1,
Bruce M. Fleischer
authored at least 20 papers
between 1996 and 2024.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2022
A 7-nm Four-Core Mixed-Precision AI Chip With 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling.
IEEE J. Solid State Circuits, 2022
2021
A 7nm 4-Core AI Chip with 25.6TFLOPS Hybrid FP8 Training, 102.4TOPS INT4 Inference and Workload-Aware Throttling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
2020
A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020
2019
DLFloat: A 16-b Floating Point Format Designed for Deep Learning Training and Inference.
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019
2018
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Proceedings of the International Symposium on Low Power Electronics and Design, 2018
2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2015
IBM J. Res. Dev., 2015
2013
IEEE Trans. Computers, 2013
2011
Proceedings of the 29th IEEE VLSI Test Symposium, 2011
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2006
4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2004
2001
IBM Syst. J., 2001
1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996