Brion L. Keller

According to our database, Brion L. Keller authored at least 41 papers between 1991 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2015

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers.

Christos Papameletis, Brion L. Keller, Vivek Chickermane, Said Hamdioui, Erik Jan Marinissen

IEEE Des. Test, 2015

At-Speed Testing of Inter-Die Connections of 3D-SICs in the Presence of Shore Logic.

Konstantin Shibin, Vivek Chickermane, Brion L. Keller, Christos Papameletis, Erik Jan Marinissen

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014

Efficient testing of hierarchical core-based SOCs.

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen

Proceedings of the 2014 International Test Conference, 2014

2013

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study.

Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim

Proceedings of the 2013 IEEE International Test Conference, 2013

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers.

Christos Papameletis, Brion L. Keller, Vivek Chickermane, Erik Jan Marinissen, Said Hamdioui

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks.

Sergej Deutsch, Brion L. Keller, Vivek Chickermane, Subhasish Mukherjee, Navdeep Sood, Sandeep Kumar Goel, Ji-Jan Chen, Ashok Mehta, Frank Lee, Erik Jan Marinissen

Proceedings of the 2012 IEEE International Test Conference, 2012

2011

Automation of 3D-DfT Insertion.

Sergej Deutsch, Vivek Chickermane, Brion L. Keller, Subhasish Mukherjee, Mario Konijnenburg, Erik Jan Marinissen, Sandeep Kumar Goel

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Reduction of Test Data Volume and Improvement of Diagnosability Using Hybrid Compression.

Anis Uzzaman, Brion L. Keller, Brian Foutz, Sandeep Bhatia, Thomas Bartenstein, Masayuki Arai, Kazuhiko Iwasaki

IEICE Trans. Inf. Syst., 2010

Low cost at-speed testing using On-Product Clock Generation compatible with test compression.

Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise

Proceedings of the 2011 IEEE International Test Conference, 2010

2009

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test.

Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai

J. Low Power Electron., 2009

CTL and Its Usage in the EDA Industry.

Rohit Kapur, Paul Reuter, Sandeep Bhatia, Brion L. Keller

IEEE Des. Test Comput., 2009

Capture power reduction using clock gating aware test generation.

Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Prashant Narang

Proceedings of the 2009 IEEE International Test Conference, 2009

A Partially-Exhaustive Gate Transition Fault Model.

Brion L. Keller, Dale Meehl, Anis Uzzaman, Richard Billings

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?.

Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Anis Uzzaman

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Optimizing Test Data Volume Using Hybrid Compression.

Brion L. Keller, Sandeep Bhatia, Thomas Bartenstein, Brian Foutz, Anis Uzzaman

Proceedings of the 17th IEEE Asian Test Symposium, 2008

Test Generation for State Retention Logic.

Krishna Chakravadhanula, Vivek Chickermane, Brion L. Keller, Patrick R. Gallagher Jr., Steven Gregor

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation.

Anis Uzzaman, Bibo Li, Thomas J. Snethen, Brion L. Keller, Gary Grise

Proceedings of the 2007 IEEE International Test Conference, 2007

Using Programmable On-Product Clock Generation (OPCG) for Delay Test.

Brion L. Keller, Anis Uzzaman, Bibo Li, Thomas J. Snethen

Proceedings of the 16th Asian Test Symposium, 2007

A Review of Power Strategies for DFT and ATPG.

Brion L. Keller, Tom Jackson, Anis Uzzaman

Proceedings of the 16th Asian Test Symposium, 2007

2006

OCI: Open Compression Interface.

Bruce Cory, Rohit Kapur, Mick Tegethoff, Mark Kassab, Brion L. Keller, Kee Sup Kim, Dwayne Burek, Steven F. Oakland, Benoit Nadeau-Dostie

Proceedings of the 2006 IEEE International Test Conference, 2006

A Scalable Architecture for On-Chip Compression: Options and Trade-Offs.

Anis Uzzaman, Brion L. Keller, Vivek Chickermane

Proceedings of the 15th Asian Test Symposium, 2006

2005

Use of MISRs for compression and diagnostics.

Brion L. Keller, Thomas Bartenstein

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Encounter test OPMISR⁺ on-chip compression.

Brion L. Keller

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Low Cost Delay Testing of Nanometer SoCs Using On-Chip Clocking and Test Compression.

Hiroyuki Nakamura, Akio Shirokane, Yoshihito Nishizaki, Anis Uzzaman, Vivek Chickermane, Brion L. Keller, Tsutomu Ube, Yoshihiko Terauchi

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Practical Aspects of Delay Testing for Nanometer Chips.

Vivek Chickermane, Brion L. Keller, Kevin McCauley, Anis Uzzaman

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

An Economic Analysis and ROI Model for Nanometer Test.

Brion L. Keller, Mick Tegethoff, Thomas Bartenstein, Vivek Chickermane

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Channel Masking Synthesis for Efficient On-Chip Test Compression.

Vivek Chickermane, Brian Foutz, Brion L. Keller

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002

Extending OPMISR beyond 10x Scan Test Efficiency.

Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion L. Keller, David Scott, Bernd Könemann, Takeshi Onodera

IEEE Des. Test Comput., 2002

2001

CTL the language for describing core-based test.

Rohit Kapur, Maurice Lousberg, Tony Taylor, Brion L. Keller, Paul Reuter, Douglas Kay

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

OPMISR: the foundation for compressed ATPG vectors.

Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Brion L. Keller, Bernd Könemann, Andrej Ferko

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

High Performance Parallel Fault Simulation.

Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

A SmartBIST Variant with Guaranteed Encoding.

Bernd Könemann, Carl Barnhart, Brion L. Keller, Thomas J. Snethen, Owen Farnsworth, Donald L. Wheater

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count.

Robert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Effective parallel processing techniques for the generation of test data for a logic built-in self test system.

Paul Chang, Brion L. Keller, Sarala Paliwal

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Using STIL to describe embedded core test requirements.

Brion L. Keller

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Design and Implementation of a Parallel Weighted Random Pattern and Logic Built in Self Test Algorithm.

Paul Chang, Brion L. Keller, Sarala Paliwal

Proceedings of the IEEE International Conference On Computer Design, 1999

1998

ATPG in practical and non-traditional applications.

Brion L. Keller, Kevin McCauley, Joseph Swenton, James Youngs

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1996

Test methodologies and design automation for IBM ASICs.

Pamela S. Gillis, Tom S. Guzowski, Brion L. Keller, Randal H. Kerr

IBM J. Res. Dev., 1996

1992

Delay Test: The Next Frontier for LSSD Test Systems.

Bernd Könemann, J. Barlow, Paul Chang, R. Gabrielson, C. Goertz, Brion L. Keller, Kevin McCauley, J. Tischer, Vijay S. Iyengar, Barry K. Rosen, T. Williams

Proceedings of the Proceedings IEEE International Test Conference 1992, 1992

1991

The Compiled Logic Simulator.

Brion L. Keller, David P. Carlson, William Maloney

IEEE Des. Test Comput., 1991

Design Automation of Test for the EX/9000^TM Series Processors.

Brion L. Keller, David A. Haynes

Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991