Brian Young
According to our database1,
Brian Young
authored at least 28 papers
between 1996 and 2017.
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Bibliography
2017
A 5GHz Digital Fractional-N PLL Using a 1-bit Delta-Sigma Frequency-to-Digital Converter in 65 nm CMOS.
IEEE J. Solid State Circuits, 2017
2015
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop.
IEEE J. Solid State Circuits, 2014
IEEE J. Solid State Circuits, 2014
A Noise-Shaping Time-to-Digital Converter Using Switched-Ring Oscillators - Analysis, Design, and Measurement Techniques.
IEEE J. Solid State Circuits, 2014
A 5 Gb/s, 10 ns Power-On-Time, 36 µW Off-State Power, Fast Power-On Transmitter for Energy Proportional Links.
IEEE J. Solid State Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
2013
IEEE J. Solid State Circuits, 2013
A 2.5GHz 2.2mW/25µW on/off-state power 2psrms-long-term-jitter digital clock multiplier with 3-reference-cycles power-on time.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 10th IEEE International Symposium on Biomedical Imaging: From Nano to Macro, 2013
2012
A 16-mW 78-dB SNDR 10-MHz BW CT Delta Sigma ADC Using Residue-Cancelling VCO-Based Quantizer.
IEEE J. Solid State Circuits, 2012
Proceedings of the Medical Image Computing and Computer-Assisted Intervention - MICCAI 2012, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 13b 315fsrms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 1.5GHz 890μW digital MDLL with 400fsrms integrated jitter, -55.6dBc reference spur and 20fs/mV supply-noise sensitivity using 1b TDC.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
A 0.7-to-3.5 GHz 0.6-to-2.8 mW Highly Digital Phase-Locked Loop With Bandwidth Tracking.
IEEE J. Solid State Circuits, 2011
A TDC-Less 7 mW 2.5 Gb/s Digital CDR With Linear Loop Dynamics and Offset-Free Data Recovery.
IEEE J. Solid State Circuits, 2011
A 0.4-to-3 GHz Digital PLL With PVT Insensitive Supply Noise Cancellation Using Deterministic Background Calibration.
IEEE J. Solid State Circuits, 2011
A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 0.4-to-3GHz digital PLL with supply-noise cancellation using deterministic background calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
A 2.4ps resolution 2.1mW second-order noise-shaped time-to-digital converter with 3.2ns range in 1MHz bandwidth.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2004
Proceedings of the Workshop Frontiers in Corpus Annotation@HLT-NAACL 2004, 2004
Proceedings of the Fourth International Conference on Language Resources and Evaluation, 2004
Proceedings of the Fourth International Conference on Language Resources and Evaluation, 2004
2000
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
1996
Effectiveness of Individual and Dyadic Training Protocols: The Influence of Trainee Interaction Anxiety.
Hum. Factors, 1996