Brian S. Leibowitz

According to our database1, Brian S. Leibowitz authored at least 18 papers between 1997 and 2015.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology.
IEEE J. Solid State Circuits, 2015

2014
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering.
Proceedings of the Symposium on VLSI Circuits, 2014

2013
A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm.
IEEE J. Solid State Circuits, 2013

2012
A 2.3-4GHz injection-locked clock multiplier with 55.7% lock range and 10-ns power-on.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques.
IEEE J. Solid State Circuits, 2011

Power-efficient I/O design considerations for high-bandwidth applications.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.
IEEE J. Solid State Circuits, 2010

Equalizer design and performance trade-offs in ADC-based serial links.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Simulation and Analysis of Random Decision Errors in Clocked Comparators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.
IEEE J. Solid State Circuits, 2009

2008
Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric.
IEEE J. Solid State Circuits, 2008

Impulse sensitivity function analysis of periodic circuits.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Characterization of random decision errors in clocked comparators.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2005
A 256-element CMOS imaging receiver for free-space optical communication.
IEEE J. Solid State Circuits, 2005

2003
Toward a wireless optical communication link between two small unmanned aerial vehicles.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

1997
Using tactile and visual sensing with a robotic hand.
Proceedings of the 1997 IEEE International Conference on Robotics and Automation, 1997


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