Brian S. Cherkauer

According to our database, Brian S. Cherkauer authored at least 10 papers between 1993 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2009

A 65 nm 2-Billion Transistor Quad-Core Itanium Processor.

Blaine A. Stackhouse, Sal Bhimji, Chris Bostak, Dave Bradley, Brian S. Cherkauer, Jayen Desai, Erin Francom, Mike Gowan, Paul E. Gronowski, Dan Krueger, Charles Morganti, Steve Troyer

IEEE J. Solid State Circuits, 2009

2008

A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor.

Blaine A. Stackhouse, Brian S. Cherkauer, Michael K. Gowan, Paul E. Gronowski, Chris Lyles

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache.

Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora

IEEE J. Solid State Circuits, 2007

2004

Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache.

Stefan Rusu, Harry Muljono, Brian S. Cherkauer

IEEE Micro, 2004

2003

A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache.

Stefan Rusu, Jason Stinson, Simon Tam, Justin Leung, Harry Muljono, Brian S. Cherkauer

IEEE J. Solid State Circuits, 2003

1995

Design of tapered buffers with local interconnect capacitance.

Brian S. Cherkauer, Eby G. Friedman

IEEE J. Solid State Circuits, February, 1995

A unified design methodology for CMOS tapered buffers.

Brian S. Cherkauer, Eby G. Friedman

IEEE Trans. Very Large Scale Integr. Syst., 1995

1994

Channel width tapering of serially connected MOSFET's with emphasis on power dissipation.

Brian S. Cherkauer, Eby G. Friedman

IEEE Trans. Very Large Scale Integr. Syst., 1994

Unification of Speed, Power, Area & Reliability in CMOS Tapered Buffer Design.

Brian S. Cherkauer, Eby G. Friedman

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

The Effects of Channel Width Tapering on the Power Dissipation of Serially Connected MOSFETs.

Brian S. Cherkauer, Eby G. Friedman

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993