Brian P. Ginsburg

Orcid: 0000-0003-1906-025X

Affiliations:
  • Texas Instruments, Dallas, TX, USA
  • Massachusetts Institute of Technology, Cambridge, MA, USA (former)


According to our database1, Brian P. Ginsburg authored at least 22 papers between 2005 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2021
Introduction to the Special Issue on the 2020 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2021


2020
Introduction to the Special Issue on the 2019 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2020

2019

2018

F3: Circuits and architectures for wireless sensing, radar and imaging.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
Introduction to the Special Issue on the 2016 Symposium on VLSI Circuits.
IEEE J. Solid State Circuits, 2017

Session 17 overview: TX and RX building blocks.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Session 25 overview: Mm-Wave and THz sensing.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2014
A 160 GHz Pulsed Radar Transceiver in 65 nm CMOS.
IEEE J. Solid State Circuits, 2014

2013
An 8-Bit Single-Ended Ultra-Low-Power SAR ADC With a Novel DAC Switching Method and a Counter-Based Digital Control Circuitry.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2009
Low-Power Impulse UWB Architectures and Circuits.
Proc. IEEE, 2009

2008
Highly Interleaved 5-bit, 250-MSample/s, 1.2-mW ADC With Redundant Channels in 65-nm CMOS.
IEEE J. Solid State Circuits, 2008

Highly Interleaved 5b 250MS/s ADC with Redundant Channels in 65nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

The mixed signal optimum energy point: voltage and parallelism.
Proceedings of the 45th Design Automation Conference, 2008

2007
Energy-efficient analog-to-digital conversion for ultra-wideband radio.
PhD thesis, 2007

500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC.
IEEE J. Solid State Circuits, 2007

Dual Time-Interleaved Successive Approximation Register ADCs for an Ultra-Wideband Receiver.
IEEE J. Solid State Circuits, 2007

2005
System design considerations for ultra-wideband communication.
IEEE Commun. Mag., 2005

An energy-efficient charge recycling approach for a SAR converter with capacitive DAC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Direct Conversion Pulsed UWB Transceiver Architecture.
Proceedings of the 2005 Design, 2005

Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005


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