Brian L. Ji

According to our database, Brian L. Ji authored at least 5 papers between 1998 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2015

In-Line-Test of Variability and Bit-Error-Rate of HfOx-Based Resistive Memory.

Brian L. Ji, H. Li, Q. Ye, S. Gausepohl, S. Deora, Dmitry Veksler, S. Vivekanand, H. Chong, H. Stamper, T. Burroughs, C. Johnson, M. Smalley, S. Bennett, V. Kaushik, J. Piccirillo, M. Rodgers, M. Passaro, M. Liehr

CoRR, 2015

2010

Practical Strategies for Power-Efficient Computing Technologies.

Leland Chang, David J. Frank, Robert K. Montoye, Steven J. Koester, Brian L. Ji, Paul W. Coteus, Robert H. Dennard, Wilfried Haensch

Proc. IEEE, 2010

2006

High-performance CMOS variability in the 65-nm regime and beyond.

Kerry Bernstein, David J. Frank, Anne E. Gattiker, Wilfried Haensch, Brian L. Ji, Sani R. Nassif, Edward J. Nowak, Dale J. Pearson, Norman J. Rohrer

IBM J. Res. Dev., 2006

2005

A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization.

Troy J. Beukema, Michael Sorna, Karl Selander, Steven Zier, Brian L. Ji, Phil Murfet, James Mason, Woogeun Rhee, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes

IEEE J. Solid State Circuits, 2005

1998

A 220-mm², four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture.

Toshiaki Kirihata, Martin Gall, Kohji Hosokawa, Jean-Marc Dortu, Hing Wong, Peter Pfefferl, Brian L. Ji, Oliver Weinfurtner, John K. DeBrosse, Hartmud Terletzki, Manfred Selz, Wayne Ellis, Matthew R. Wordeman, Oliver Kiehl

IEEE J. Solid State Circuits, 1998