Brian J. Larivee

According to our database1, Brian J. Larivee authored at least 4 papers between 2005 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2009
Digital Background-Calibration Algorithm for "Split ADC" Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2006
Comments on 'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC".
IEEE J. Solid State Circuits, 2006

2005
"Split ADC" architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC.
IEEE J. Solid State Circuits, 2005

A CMOS-integrated microinstrument for trace detection of heavy metals.
IEEE J. Solid State Circuits, 2005


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