Brian Elies

According to our database1, Brian Elies authored at least 6 papers between 2012 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
16MHz FRAM Micro-Controller with a Low-Cost Sub-1μA Embedded Piezo-Electric Strain Sensor for ULP Motion Detection.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017
A Non-Interleaved 12-b 330-MS/s Pipelined-SAR ADC With PVT-Stabilized Dynamic Amplifier Achieving Sub-1-dB SNDR Variation.
IEEE J. Solid State Circuits, 2017

An 8b 1.39GS/S 0.85V two-step ADC with background comparator offset calibration.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variation.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

2012
An 85dB SFDR 67dB SNDR 8OSR 240MS/s ΔΣ ADC with nonlinear memory error calibration.
Proceedings of the Symposium on VLSI Circuits, 2012


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