Brian Cline

According to our database¹, Brian Cline authored at least 41 papers between 2006 and 2022.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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PhD thesis

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Links

On csauthors.net:

Bibliography

2022

Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

System technology co-optimization and design challenges for 3D IC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors.

[BibT_eX]

[DOI]

Lingjun Zhu

Lennart Bamberg

Sai Surya Kiran Pentapati

IEEE Trans. Very Large Scale Integr. Syst., 2021

Device-to-System Performance Evaluation: from Transistor/Interconnect Modeling to VLSI Physical Design and Neural-Network Predictor.

[BibT_eX]

[DOI]

CoRR, 2021

Power Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

A 64-Bit Arm CPU at Cryogenic temperatures: Design Technology Co-Optimization for Power and Performance.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

3D-Split SRAM: Enabling Generational Gains in Advanced CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020

Stack up your chips: Betting on 3D integration to augment Moore's Law scaling.

[BibT_eX]

[DOI]

CoRR, 2020

2019

System-Level Power Delivery Network Analysis and Optimization for Monolithic 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Enhanced 3D Implementation of an Arm<sup>®</sup> Cortex<sup>®</sup>-A Microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

2018

Standard Cell Library Design and Optimization Methodology for ASAP7 PDK.

[BibT_eX]

[DOI]

CoRR, 2018

Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's rule.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Impact and Design Guideline of Monolithic 3-D IC at the 7-nm Technology Node.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Redundant Local-Loop Insertion for Unidirectional Routing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Impact of FinFET on Near-Threshold Voltage Scalability.

[BibT_eX]

[DOI]

Nathaniel Ross Pinckney

IEEE Des. Test, 2017

Frequency and time domain analysis of power delivery network for monolithic 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

DTCO for DSA-MP Hybrid Lithography with Double-BCP Materials in Sub-7nm Node.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper).

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

ASAP7: A 7-nm finFET predictive process design kit.

[BibT_eX]

[DOI]

Chandarasekaran Ramamurthy

Greg Yeric

Microelectron. J., 2016

Predicting future complementary metal-oxide-semiconductor technology - challenges and approaches.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2016

Welcome.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Monolithic 3D IC design: Power, performance, and area impact at 7nm.

[BibT_eX]

[DOI]

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Four-tier Monolithic 3D ICs: Tier Partitioning Methodology and Power Benefit Study.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Cascade2D: A design-aware partitioning approach to monolithic 3D IC with 2D commercial tools.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Near-threshold computing in FinFET technologies: opportunities for improved voltage scalability.

[BibT_eX]

[DOI]

Nathaniel Ross Pinckney

Proceedings of the 53rd Annual Design Automation Conference, 2016

Match-making for monolithic 3D IC: finding the right technology node.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Circuit design perspectives for Ge FinFET at 10nm and beyond.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Power benefit study of monolithic 3D IC at the 7nm technology node.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

2014

Physical design and FinFETs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Physical Design, 2014

DFM is dead - Long live DFM.

[BibT_eX]

[DOI]

Robert C. Aitken

David Pietromonaco

Brian Cline

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

The past present and future of design-technology co-optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

Design benchmarking to 7nm with FinFET predictive technology models.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Exploring sub-20nm FinFET design with predictive technology models.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010

Mechanical Stress Aware Optimization for Leakage Power Reduction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2008

Exploring Variability and Performance in a Sub-200-mV Processor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

Stress aware layout optimization.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Symposium on Physical Design, 2008

STEEL: a technique for stress-enhanced standard cell library design.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Transistor-Specific Delay Modeling for SSTA.

[BibT_eX]

[DOI]

Savithri Sundareswaran

Proceedings of the Design, Automation and Test in Europe, 2008

Leakage power reduction using stress-enhanced layouts.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2006

Analysis and modeling of CD variation for statistical static timing.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Brian Cline

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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