Brian C. Richards

Orcid: 0000-0001-9084-5282

According to our database1, Brian C. Richards authored at least 24 papers between 1987 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
HDBinaryCore: A 28nm 2048-bit Hyper-Dimensional biosignal classifier achieving 25 nJ/prediction for EMG hand-gesture recognition.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

2022
An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET.
IEEE J. Solid State Circuits, 2022

2021
4.3 An Eight-Core 1.44GHz RISC-V Vector Machine in 16nm FinFET.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance.
IEEE J. Solid State Circuits, 2019

2018

2017
A 0.37mm<sup>2</sup> LTE/Wi-Fi compatible, memory-based, runtime-reconfigurable 2<sup>n</sup>3<sup>m</sup>5<sup>k</sup> FFT accelerator integrated with a RISC-V core in 16nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
An Agile Approach to Building RISC-V Microprocessors.
IEEE Micro, 2016

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.
IEEE J. Solid State Circuits, 2016

2015
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.
Proceedings of the Symposium on VLSI Circuits, 2015

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2012
Chisel: constructing hardware in a Scala embedded language.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
A 2 Gb/s 5.6 mW Digital LOS/NLOS Equalizer for the 60 GHz Band.
IEEE J. Solid State Circuits, 2011

2009
A 1.5GS/s 4096-point digital spectrum analyzer for space-borne applications.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2007
ASIC Design and Verification in an FPGA Environment.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2004
Describing MIMO designs for rapid prototyping in the BEE environment.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

2003
Designing BEE: A Hardware Emulation Engine for Signal Processing in Low-Power Wireless Applications.
EURASIP J. Adv. Signal Process., 2003

Rapid Design and Analysis of Communication Systems Using the BEE Hardware Emulation Environment.
Proceedings of the 14th IEEE International Workshop on Rapid System Prototyping (RSP 2003), 2003

Implementation of BEE: a real-time large-scale hardware emulation engine.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

1995
Design of Wireless Portable Systems.
Proceedings of the COMPCON '95: Technologies for the Information Superhighway, 1995

A prototype user interface for a mobile multimedia terminal.
Proceedings of the Human Factors in Computing Systems, 1995

1994
Research challenges in wireless multimedia.
Proceedings of the 5th IEEE International Symposium on Personal, 1994

1991
An integrated CAD system for algorithm-specific IC design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1990
Hardware for Hidden Markov-Model-Based, Large-Vocabulary Real-Time Speech Recognition.
Proceedings of the Speech and Natural Language: Proceedings of a Workshop Held at Hidden Valley, 1990

1987
A parameterized VLSI video-rate histogram processor.
Proceedings of the IEEE International Conference on Acoustics, 1987


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