Brett H. Meyer

According to our database, Brett H. Meyer authored at least 83 papers between 2005 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Automatic Pruning of Fine-tuning Datasets for Transformer-based Language Models.

Mohammadreza Tayaranian, Seyyed Hasan Mozafari, Brett H. Meyer, James J. Clark, Warren J. Gross

CoRR, 2024

Faster Inference of Integer SWIN Transformer by Removing the GELU Activation.

Mohammadreza Tayaranian, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross

CoRR, 2024

AdCorDA: Classifier Refinement via Adversarial Correction and Domain Adaptation.

Lulan Shen, Ali Edalati, Brett H. Meyer, Warren J. Gross, James J. Clark

CoRR, 2024

Robustness to distribution shifts of compressed networks for edge devices.

Lulan Shen, Ali Edalati, Brett H. Meyer, Warren J. Gross, James J. Clark

CoRR, 2024

Intermediate Layer Distillation with the Reused Teacher Classifier: A Study on the Importance of the Classifier of Attention-based Models.

Hang Zhang, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross

Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2024, 2024

2023

PipeBERT: High-throughput BERT Inference for ARM Big.LITTLE Multi-core Processors.

Hung-Yang Chang, Seyyed Hasan Mozafari, Cheng Chen, James J. Clark, Brett H. Meyer, Warren J. Gross

J. Signal Process. Syst., July, 2023

DT-DS: CAN Intrusion Detection with Decision Tree Ensembles.

Jarul Mehta, Guillaume Richard, Loren Lugosch, Derek Yu, Brett H. Meyer

ACM Trans. Cyber Phys. Syst., January, 2023

SSS3D: Fast Neural Architecture Search For Efficient Three-Dimensional Semantic Segmentation.

Olivier Therrien, Marihan Amein, Zhuoran Xiong, Warren J. Gross, Brett H. Meyer

CoRR, 2023

FMAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation.

Zhuoran Xiong, Marihan Amein, Olivier Therrien, Warren J. Gross, Brett H. Meyer

CoRR, 2023

Training Acceleration of Frequency Domain CNNs Using Activation Compression.

Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

High-Throughput Edge Inference for BERT Models via Neural Architecture Search and Pipeline.

Hung-Yang Chang, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Fast Fine-Tuning Using Curriculum Domain Adaptation.

Lulan Shen, Ibtihel Amara, Ruofeng Li, Brett H. Meyer, Warren J. Gross, James J. Clark

Proceedings of the 20th Conference on Robots and Vision, 2023

Efficient 1D Grouped Convolution for PyTorch a Case Study: Fast On-Device Fine-Tuning for SqueezeBERT.

Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer

Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

2022

BD-KD: Balancing the Divergences for Online Knowledge Distillation.

Ibtihel Amara, Nazanin Mohammadi Sepahvand, Brett H. Meyer, Warren J. Gross, James J. Clark

CoRR, 2022

Efficient Fine-Tuning of Compressed Language Models with Learners.

Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross

CoRR, 2022

Standard Deviation-Based Quantization for Deep Neural Networks.

Amir Ardakani, Arash Ardakani, Brett H. Meyer, James J. Clark, Warren J. Gross

CoRR, 2022

BERTPerf: Inference Latency Predictor for BERT on ARM big.LITTLE Multi-Core Processors.

M. Abdelgawad, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross

Proceedings of the IEEE Workshop on Signal Processing Systems, 2022

Efficient Fine-Tuning of BERT Models on the Edge.

Danilo Vucetic, Mohammadreza Tayaranian, Maryam Ziaeefard, James J. Clark, Brett H. Meyer, Warren J. Gross

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

CES-KD: Curriculum-based Expert Selection for Guided Knowledge Distillation.

Ibtihel Amara, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark

Proceedings of the 26th International Conference on Pattern Recognition, 2022

Conjugate Adder Net (CAddNet) - a Space-Efficient Approximate CNN.

Lulan Shen, Maryam Ziaeefard, Brett H. Meyer, Warren J. Gross, James J. Clark

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 2022

Work-in-Progress: Utilizing latency and accuracy predictors for efficient hardware-aware NAS.

Negin Firouzian, Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022

Work-in-Progress: SuperNAS: Fast Multi-Objective SuperNet Architecture Search for Semantic Segmentation.

Marihan Amein, Zhuoran Xiong, Olivier Therrien, Brett H. Meyer, Warren J. Gross

Proceedings of the International Conference on Compilers, 2022

Fast Heterogeneous Task Mapping for Reducing Edge DNN Latency.

Murray L. Kornelsen, Seyyed Hasan Mozafari, James J. Clark, Brett H. Meyer, Warren J. Gross

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021

Worst-case Execution Time Calculation for Query-based Monitors by Witness Generation.

Márton Búr, Kristóf Marussy, Brett H. Meyer, Dániel Varró

ACM Trans. Embed. Comput. Syst., 2021

A Design Framework for Invertible Logic.

Naoya Onizawa, Kaito Nishino, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Implementing Convolutional Neural Networks Using Hartley Stochastic Computing With Adaptive Rate Feature Map Compression.

Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer

IEEE Open J. Circuits Syst., 2021

Hardware-Aware Design for Edge Intelligence.

Warren J. Gross, Brett H. Meyer, Arash Ardakani

IEEE Open J. Circuits Syst., 2021

Hartley Stochastic Computing For Convolutional Neural Networks.

Seyyed Hasan Mozafari, James J. Clark, Warren J. Gross, Brett H. Meyer

Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

2020

In-Hardware Training Chip Based on CMOS Invertible Logic for Machine Learning.

Naoya Onizawa, Sean C. Smithson, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Hot sparing for lifetime-chip-performance and cost improvement in application specific SIMT processors.

Seyyed Hasan Mozafari, Brett H. Meyer

Des. Autom. Embed. Syst., 2020

Surprisal-Triggered Conditional Computation with Neural Networks.

Loren Lugosch, Derek Nowrouzezahrai, Brett H. Meyer

CoRR, 2020

Using Speech Synthesis to Train End-To-End Spoken Language Understanding Models.

Loren Lugosch, Brett H. Meyer, Derek Nowrouzezahrai, Mirco Ravanelli

Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Probabilistic Sequential Multi-Objective Optimization of Convolutional Neural Networks.

Zixuan Yin, Warren J. Gross, Brett H. Meyer

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Partitioning and Selection of Data Consistency Mechanisms for Multicore Real-Time Systems.

Zaid Al-bayati, Youcheng Sun, Haibo Zeng, Marco Di Natale, Qi Zhu, Brett H. Meyer

ACM Trans. Embed. Comput. Syst., 2019

Efficient CMOS Invertible Logic Using Stochastic Computing.

Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Takahiro Hanyu

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Characterizing the Effectiveness of Hot Sparing on Cost and Performance-per-Watt in Application Specific SIMT.

Seyyed Hasan Mozafari, Brett H. Meyer

Integr., 2019

ARINC-825TBv2: A Hardware-in-the-Ioop Simulation Platform for Aerospace Security Research.

Derek Yu, Michael Vaquier, Evan Laflamme, Gabrielle Doucette-Poirier, Justin Tremblay, Brett H. Meyer

Proceedings of the 30th International Workshop on Rapid System Prototyping, 2019

Learning Recurrent Binary/Ternary Weights.

Arash Ardakani, Zhengyun Ji, Sean C. Smithson, Brett H. Meyer, Warren J. Gross

Proceedings of the 7th International Conference on Learning Representations, 2019

2018

Efficient Performance Evaluation of Multi-Core SIMT Processors with Hot Redundancy.

Seyyed Hasan Mozafari, Brett H. Meyer

IEEE Trans. Emerg. Top. Comput., 2018

Mapping and Scheduling Mixed-Criticality Systems with On-Demand Redundancy.

Jonah Caplan, Zaid Al-bayati, Haibo Zeng, Brett H. Meyer

IEEE Trans. Computers, 2018

Study of Stochastic Invertible Multiplier Designs.

Kaito Nishino, Sean C. Smithson, Naoya Onizawa, Brett H. Meyer, Warren J. Gross, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

Area, Throughput, and Power Trade-Offs for FPGA- and ASIC-Based Execution Stream Compression.

Maria Isabel Mera, Jonah Caplan, Seyyed Hasan Mozafari, Brett H. Meyer, Peter A. Milder

ACM Trans. Embed. Comput. Syst., 2017

Multi-armed bandits for efficient lifetime estimation in MPSoC design.

Calvin Ma, Aditya Mahajan, Brett H. Meyer

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures.

Runjie Zhang, Brett H. Meyer, Ke Wang, Mircea R. Stan, Kevin Skadron

IEEE Trans. Very Large Scale Integr. Syst., 2016

Stochastic Computing Can Improve Upon Digital Spiking Neural Networks.

Sean C. Smithson, Kaushik Boga, Arash Ardakani, Brett H. Meyer, Warren J. Gross

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Sparse-Clustered Network with Selective Decoding for Internet Traffic Classification.

Scott Dickson Dagondon, Warren J. Gross, Brett H. Meyer

Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016

Neural networks designing neural networks: multi-objective hyper-parameter optimization.

Sean C. Smithson, Guang Yang, Warren J. Gross, Brett H. Meyer

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components.

Dimitrios Stamoulis, Simone Corbetta, Dimitrios Rodopoulos, Pieter Weckx, Peter Debacker, Brett H. Meyer, Ben Kaczer, Praveen Raghavan, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Bounding error detection latency in safety critical systems with enhanced Execution Fingerprinting.

Mojing Liu, Brett H. Meyer

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failures.

Zaid Al-bayati, Brett H. Meyer, Haibo Zeng

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

A four-mode model for efficient fault-tolerant mixed-criticality systems.

Zaid Al-bayati, Jonah Caplan, Brett H. Meyer, Haibo Zeng

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Techniques for on-demand structural redundancy for massively parallel processor arrays.

Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer

J. Syst. Archit., 2015

Task placement and selection of data consistency mechanisms for real-time multicore applications.

Zaid Al-bayati, Youcheng Sun, Haibo Zeng, Marco Di Natale, Qi Zhu, Brett H. Meyer

Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Transient voltage noise in charge-recycled power delivery networks for many-layer 3D-IC.

Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea R. Stan

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models.

Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Francky Catthoor, Zeljko Zilic

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Yield-aware Performance-Cost Characterization for Multi-Core SIMT.

Seyyed Hasan Mozafari, Brett H. Meyer, Kevin Skadron

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

RotR: Rotational redundant task mapping for fail-operational MPSoCs.

Badrun Nahar, Brett H. Meyer

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

Hot spare components for performance-cost improvement in multi-core SIMT.

Seyyed Hasan Mozafari, Brett H. Meyer

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC.

Runjie Zhang, Kaushik Mazumdar, Brett H. Meyer, Ke Wang, Kevin Skadron, Mircea R. Stan

Proceedings of the 52nd Annual Design Automation Conference, 2015

A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays.

Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer

Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

2014

Cost-effective lifetime and yield optimization for NoC-based MPSoCs.

Brett H. Meyer, Adam S. Hartman, Donald E. Thomas

ACM Trans. Design Autom. Electr. Syst., 2014

Architecture implications of pads as a scarce resource.

Runjie Zhang, Ke Wang, Brett H. Meyer, Mircea R. Stan, Kevin Skadron

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Linear regression techniques for efficient analysis of transistor variability.

Dimitrios Stamoulis, Dimitrios Rodopoulos, Brett H. Meyer, Dimitrios Soudris, Zeljko Zilic

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

MB-FICA: multi-bit fault injection and coverage analysis.

Chen Jiang, Mojing Liu, Brett H. Meyer

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Flexibility and Circuit Overheads in Reconfigurable SIMD/MIMD Systems.

Saad Arrabi, D. Moore, L. Wang, Kevin Skadron, Benton H. Calhoun, John C. Lach, Brett H. Meyer

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Trade-offs in execution signature compression for reliable processor systems.

Jonah Caplan, Maria Isabel Mera, Peter A. Milder, Brett H. Meyer

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization.

Ke Wang, Brett H. Meyer, Runjie Zhang, Mircea R. Stan, Kevin Skadron

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Walking pads: Fast power-supply pad-placement optimization.

Ke Wang, Brett H. Meyer, Runjie Zhang, Kevin Skadron, Mircea R. Stan

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Evaluating Overheads of Multibit Soft-Error Protection in the Processor Core.

Lukasz G. Szafaryn, Brett H. Meyer, Kevin Skadron

IEEE Micro, 2013

Architectural implications of spatial thermal filtering.

Karthik Sankaranarayanan, Brett H. Meyer, Wei Huang, Robert J. Ribando, Hossein Haj-Hariri, Mircea R. Stan, Kevin Skadron

Integr., 2013

2012

ArchFP: Rapid prototyping of pre-RTL floorplans.

Gregory G. Faust, Runjie Zhang, Kevin Skadron, Mircea R. Stan, Brett H. Meyer

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

2011

Thermal benefit of multi-core floorplanning: A limits study.

Karthik Sankaranarayanan, Brett H. Meyer, Mircea R. Stan, Kevin Skadron

Sustain. Comput. Informatics Syst., 2011

Reducing the cost of redundant execution in safety-critical systems using relaxed dedication.

Brett H. Meyer, Nishant J. George, Benton H. Calhoun, John C. Lach, Kevin Skadron

Proceedings of the Design, Automation and Test in Europe, 2011

Cost-effective safety and fault localization using distributed temporal redundancy.

Brett H. Meyer, Benton H. Calhoun, John C. Lach, Kevin Skadron

Proceedings of the 14th International Conference on Compilers, 2011

2010

Slack allocation for yield improvement in NoC-based MPSoCs.

Brett H. Meyer, Adam S. Hartman, Donald E. Thomas

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Temperature-to-power mapping.

Zhenyu Qi, Brett H. Meyer, Wei Huang, Robert J. Ribando, Kevin Skadron, Mircea R. Stan

Proceedings of the 28th International Conference on Computer Design, 2010

Cost-effective slack allocation for lifetime improvement in NoC-based MPSoCs.

Brett H. Meyer, Adam S. Hartman, Donald E. Thomas

Proceedings of the Design, Automation and Test in Europe, 2010

A case for lifetime-aware task mapping in embedded chip multiprocessors.

Adam S. Hartman, Donald E. Thomas, Brett H. Meyer

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

2009

Rethinking the synthesis of buses, data mapping, and memory allocation for MPSoC.

Brett H. Meyer, Donald E. Thomas

Des. Autom. Embed. Syst., 2009

2007

Amdahl's Law Revisited for Single Chip Systems.

JoAnn M. Paul, Brett H. Meyer

Int. J. Parallel Program., 2007

Rethinking Automated Synthesis of MPSoC Architectures.

Brett H. Meyer, Donald E. Thomas

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC.

Brett H. Meyer, Donald E. Thomas

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2005

Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors.

Brett H. Meyer, Joshua J. Pieper, JoAnn M. Paul, Jeffrey E. Nelson, Sean M. Pieper, Anthony G. Rowe

IEEE Trans. Computers, 2005