Breeta SenGupta

According to our database, Breeta SenGupta authored at least 5 papers between 2012 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Test Flow Selection for Stacked Integrated Circuits.

Breeta SenGupta, Dimitar Nikolov, Assmitra Dash, Erik Larsson

J. Electron. Test., 2019

2017

Test Planning for Core-based Integrated Circuits under Power Constraints.

Breeta SenGupta, Dimitar Nikolov, Urban Ingelsson, Erik Larsson

J. Electron. Test., 2017

2014

Test planning and test access mechanism design for stacked chips using ILP.

Breeta SenGupta, Erik Larsson

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

2012

Scheduling Tests for 3D Stacked Chips under Power Constraints.

Breeta SenGupta, Urban Ingelsson, Erik Larsson

J. Electron. Test., 2012

Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias.

Breeta SenGupta, Urban Ingelsson, Erik Larsson

Proceedings of the 25th International Conference on VLSI Design, 2012