Brandon Reagen

Orcid: 0000-0002-1932-2750

According to our database1, Brandon Reagen authored at least 62 papers between 2013 and 2024.

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Bibliography

2024
DeepReShape: Redesigning Neural Networks for Efficient Private Inference.
Trans. Mach. Learn. Res., 2024

AERO: Softmax-Only LLMs for Efficient Private Inference.
CoRR, 2024

ReLU's Revival: On the Entropic Overload in Normalization-Free Large Language Models.
CoRR, 2024

Osiris: A Systolic Approach to Accelerating Fully Homomorphic Encryption.
CoRR, 2024

NTTSuite: Number Theoretic Transform Benchmarks for Accelerating Encrypted Computation.
CoRR, 2024

CiFlow: Dataflow Analysis and Optimization of Key Switching for Homomorphic Encryption.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2024

SZKP: A Scalable Accelerator Architecture for Zero-Knowledge Proofs.
Proceedings of the 2024 International Conference on Parallel Architectures and Compilation Techniques, 2024

2023
RPU: The Ring Processing Unit.
IACR Cryptol. ePrint Arch., 2023

TREBUCHET: Fully Homomorphic Encryption Accelerator for Deep Computation.
IACR Cryptol. ePrint Arch., 2023

Orion: A Fully Homomorphic Encryption Compiler for Private Deep Neural Network Inference.
CoRR, 2023

PriViT: Vision Transformers for Fast Private Inference.
CoRR, 2023

Privacy Preserving In-memory Computing Engine.
CoRR, 2023

Design Space Exploration of Modular Multipliers for ASIC FHE accelerators.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Exploring the Efficiency of Data-Oblivious Programs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Quantifying the Overheads of Modular Multiplication.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

HAAC: A Hardware-Software Co-Design to Accelerate Garbled Circuits.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Generating High-Performance Number Theoretic Transform Implementations for Vector Architectures.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2023

Towards Fast and Scalable Private Inference.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

Characterizing and Optimizing End-to-End Systems for Private Inference.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Sphynx: A Deep Neural Network Design for Private Inference.
IEEE Secur. Priv., 2022

Impala: Low-Latency, Communication-Efficient Private Deep Learning Inference.
CoRR, 2022

Verifiable Access Control for Augmented Reality Localization and Mapping.
CoRR, 2022

Homomorphically Encrypted Computation using Stochastic Encodings.
CoRR, 2022

Selective Network Linearization for Efficient Private Inference.
Proceedings of the International Conference on Machine Learning, 2022

2021
CryptoNite: Revealing the Pitfalls of End-to-End Private Inference at Scale.
CoRR, 2021

Sisyphus: A Cautionary Tale of Using Low-Degree Polynomial Activations in Privacy-Preserving Deep Learning.
CoRR, 2021

Sphynx: ReLU-Efficient Network Design for Private Inference.
CoRR, 2021

Analysis and Mitigations of Reverse Engineering Attacks on Local Feature Descriptors.
CoRR, 2021

VIP-Bench: A Benchmark Suite for Evaluating Privacy-Enhanced Computation Frameworks.
Proceedings of the 2021 International Symposium on Secure and Private Execution Environment Design (SEED), 2021

Porcupine: a synthesizing compiler for vectorized homomorphic encryption.
Proceedings of the PLDI '21: 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2021

Circa: Stochastic ReLUs for Private Deep Learning.
Proceedings of the Advances in Neural Information Processing Systems 34: Annual Conference on Neural Information Processing Systems 2021, 2021

DeepReDuce: ReLU Reduction for Fast Private Inference.
Proceedings of the 38th International Conference on Machine Learning, 2021

Cheetah: Optimizing and Accelerating Homomorphic Encryption for Private Inference.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

Mitigating Reverse Engineering Attacks on Local Feature Descriptors.
Proceedings of the 32nd British Machine Vision Conference 2021, 2021

2020
Cheetah: Optimizations and Methods for PrivacyPreserving Inference via Homomorphic Encryption.
CoRR, 2020

CryptoNAS: Private Inference on a ReLU Budget.
Proceedings of the Advances in Neural Information Processing Systems 33: Annual Conference on Neural Information Processing Systems 2020, 2020

SoK: Opportunities for Software-Hardware-Security Codesign for Next Generation Secure Computing.
Proceedings of the HASP@MICRO 2020: Hardware and Architectural Support for Security and Privacy, 2020

RecNMP: Accelerating Personalized Recommendation with Near-Memory Processing.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

DeepRecSys: A System for Optimizing End-To-End At-Scale Neural Recommendation Inference.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

The Architectural Implications of Facebook's DNN-Based Personalized Recommendation.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020

2019
The Architectural Implications of Facebook's DNN-based Personalized Recommendation.
CoRR, 2019

MaxNVM: Maximizing DNN Storage Density and Inference Efficiency with Sparse Encoding and Error Mitigation.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Demystifying Bayesian Inference Workloads.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

Machine Learning at Facebook: Understanding Inference at the Edge.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

MASR: A Modular Accelerator for Sparse RNNs.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
Assisting High-Level Synthesis Improve SpMV Benchmark Through Dynamic Dependence Analysis.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

Weightless: Lossy weight encoding for deep neural network compression.
Proceedings of the 35th International Conference on Machine Learning, 2018

Ares: a framework for quantifying the resilience of deep neural networks.
Proceedings of the 55th Annual Design Automation Conference, 2018

On-chip deep neural network storage with multi-level eNVM.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Deep Learning for Computer Architects
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01756-8, 2017

Cognitive Computing Safety: The New Horizon for Reliability / The Design and Evolution of Deep Learning Workloads.
IEEE Micro, 2017

A Fully Integrated Battery-Powered System-on-Chip in 40-nm CMOS for Closed-Loop Control of Insect-Scale Pico-Aerial Vehicle.
IEEE J. Solid State Circuits, 2017

Methods and infrastructure in the era of accelerator-centric architectures.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A case for efficient accelerator design space exploration via Bayesian optimization.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017

Using dynamic dependence analysis to improve the quality of high-level synthesis designs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Minerva: Enabling Low-Power, Highly-Accurate Deep Neural Network Accelerators.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Fathom: reference workloads for modern deep learning methods.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

2015
The Aladdin Approach to Accelerator Design and Modeling.
IEEE Micro, 2015

A multi-chip system optimized for insect-scale flapping-wing robots.
Proceedings of the Symposium on VLSI Circuits, 2015

2014
Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

MachSuite: Benchmarks for accelerator design and customized architectures.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

2013
Quantifying acceleration: Power/performance trade-offs of application kernels in hardware.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013


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