Bradley S. Carlson

Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

2000

Power estimation for a submicron CMOS inverter driving a CRC interconnect load.

[BibT_eX]

[DOI]

Hung-Jung Chen

Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

1999

Transistor Chaining in Static CMOS Functional Cells of Arbitrary Planar Topology.

[BibT_eX]

[DOI]

Dikran S. Meliksetian

Discret. Appl. Math., 1999

1998

Parallel implementation of a unified approach to image focus and defocus analysis on the Parallel Virtual Machine.

[BibT_eX]

[DOI]

Proceedings of the Visual Information Processing VII, Orlando, FL, USA, April 13, 1998, 1998

1997

Parallel logic simulation on a network of workstations using parallel virtual machine.

[BibT_eX]

[DOI]

Maciek Kormicki

Ausif Mahmood

ACM Trans. Design Autom. Electr. Syst., 1997

Fault Tolerant Algorithms for Broadcasting on the Star Graph Network.

[BibT_eX]

[DOI]

Nai-Wei Lo

D. L. Tao

IEEE Trans. Computers, 1997

A VLSI circuit design course for practitioners and researchers.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997

Critical Voltage Transition Logic: An Ultrafast CMOS Logic Family.

[BibT_eX]

[DOI]

Zhang Zhu

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

A Unified Algorithm for the Estimation and Scheduling of Data Flow Graphs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 1996

Parallel logic simulation on a network of workstations using PVM.

[BibT_eX]

[DOI]

Maciek Kormicki

Ausif Mahmood

Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

Transistor Chaining in CMOS Leaf Cells of Planar Topology.

[BibT_eX]

[DOI]

Dikran S. Meliksetian

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

LILA: layout generation for iterative logic arrays.

[BibT_eX]

[DOI]

Qinghong Wu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

A preprocessor for improving channel routing hierarchical pin permutation.

[BibT_eX]

[DOI]

Cliff Yungchin Hou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Delay optimization of digital CMOS VLSI circuits by transistor reordering.

[BibT_eX]

[DOI]

Suh-Juch Lee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Dual Eulerian Properties of Plane Multigraphs.

[BibT_eX]

[DOI]

Dikran S. Meliksetian

SIAM J. Discret. Math., 1995

Synthesis of SEU-tolerant ASICs using concurrent error correction.

[BibT_eX]

[DOI]

Harry Hollander

Toby D. Bennett

Proceedings of the 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), 1995

1994

Improved Lower Bounds for the Scheduling Optimization Problem.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Unified Algorithm for Estimation and Scheduling in Data Path Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1993

Lower Bounds on the Iteration Time and the Number of Resources for Functional Pipelined Data Flow Graphs.

[BibT_eX]

[DOI]

Ahmed Ghouse

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering.

[BibT_eX]

[DOI]

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1991

Optimal cell generation for dual independent layout styles.

[BibT_eX]

[DOI]