Bradley McDanel

Orcid: 0000-0001-6684-8918

According to our database1, Bradley McDanel authored at least 25 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
AMUSD: Asynchronous Multi-Device Speculative Decoding for LLM Acceleration.
CoRR, 2024

2023
StitchNet: Composing Neural Networks from Pre-Trained Fragments.
Proceedings of the International Conference on Machine Learning and Applications, 2023

Dynamic Patch Sampling for Efficient Training and Dynamic Inference in Vision Transformers.
Proceedings of the International Conference on Machine Learning and Applications, 2023

2022
Accelerating Vision Transformer Training via a Patch Sampling Schedule.
CoRR, 2022

Accelerating DNN Training with Structured Data Gradient Pruning.
Proceedings of the 26th International Conference on Pattern Recognition, 2022

FAST: DNN Training Under Variable Precision Block Floating Point with Stochastic Rounding.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022

2021
Saturation RRAM Leveraging Bit-Level Sparsity Resulting from Term Quantization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Training for multi-resolution inference using reusable quantization terms.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
Term Revealing: Furthering Quantization at Run Time on Quantized DNNs.
CoRR, 2020

Term quantization: furthering quantization at run time.
Proceedings of the International Conference for High Performance Computing, 2020

2019
Full-stack Optimization for Accelerating CNNs with FPGA Validation.
CoRR, 2019

Systolic Building Block for Logic-on-Logic 3D-IC Implementations of Convolutional Neural Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Full-stack optimization for accelerating CNNs using powers-of-two weights with FPGA validation.
Proceedings of the ACM International Conference on Supercomputing, 2019

Packing Sparse Convolutional Neural Networks for Efficient Systolic Array Implementations: Column Combining Under Joint Optimization.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Maestro: A Memory-on-Logic Architecture for Coordinated Parallel Use of Many Systolic Arrays.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Mapping Systolic Arrays onto 3D Circuit Structures: Accelerating Convolutional Neural Network Inference.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

Adaptive Tiling: Applying Fixed-size Systolic Arrays To Sparse Convolutional Neural Networks.
Proceedings of the 24th International Conference on Pattern Recognition, 2018

2017
Incomplete Dot Products for Dynamic Computation Scaling in Neural Network Inference.
Proceedings of the 16th IEEE International Conference on Machine Learning and Applications, 2017

Distributed Deep Neural Networks Over the Cloud, the Edge and End Devices.
Proceedings of the 37th IEEE International Conference on Distributed Computing Systems, 2017

Embedded Binarized Neural Networks.
Proceedings of the 2017 International Conference on Embedded Wireless Systems and Networks, 2017

2016
BranchyNet: Fast inference via early exiting from deep neural networks.
Proceedings of the 23rd International Conference on Pattern Recognition, 2016

2015
Taming Wireless Fluctuations by Predictive Queuing Using a Sparse-Coding Link-State Model.
Proceedings of the 16th ACM International Symposium on Mobile Ad Hoc Networking and Computing, 2015

PNNU: Parallel Nearest-Neighbor Units for Learned Dictionaries.
Proceedings of the Languages and Compilers for Parallel Computing, 2015

Sparse Coding Trees with application to emotion classification.
Proceedings of the 2015 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2015

Outlier detection for large scale manufacturing processes.
Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData 2015), Santa Clara, CA, USA, October 29, 2015


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