Brad Vest

According to our database, Brad Vest authored at least 6 papers between 1998 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2015

Arria™ 10 device architecture.

Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Design of a high-density SoC FPGA at 20nm.

Brad Vest, Sean Atsatt, Mike Hutton

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

2004

MAX II: A low-cost, high-performance LUT-based CPLD.

Paul Leventis, Brad Vest, Mike Hutton, David M. Lewis

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Cyclone ™: a low-cost, high-performance FPGA.

Paul Leventis, Mark Chan, Michael Chan, David M. Lewis, Behzad Nouban, Giles Powell, Brad Vest, Myron Wong, Renxin Xia, John Costello

Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

1999

A 4.9 ns, 3.3 volt, 512 macrocell, CMOS PLD with hot socket protection and fast in system programming.

Brad Vest, Gwen Liang, Mark Chan, Eric Chun, Mark Fiester, Weiying Ding, Edmond Lau, Guu Lin, Behzad Nouban, Dirk Reese, Mian Smith, Nghia Tran, Stephanie Wong, Michael Woo, Myron Wong, John Costello

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability.

Dirk Reese, Eric Chun, Sammy Cheung, Edmond Lau, Michael Chu, Gwen Liang, Nghia Van Tran, Brad Vest, Richard Smolen, Minchang Liang, Seshan Sekariapuram, Behzad Nouban, Myron Wong, John Costello, John Turner

Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998