Bonnie Wang
According to our database1,
Bonnie Wang
authored at least 5 papers
between 1995 and 2020.
Collaborative distances:
Collaborative distances:
Timeline
1995
2000
2005
2010
2015
2020
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
CoRR, 2020
2005
A 90-nm FPGA I/O buffer design with 1.6-Gb/s data rate for source-synchronous system and 300-MHz clock rate for external memory interface.
IEEE J. Solid State Circuits, 2005
2004
A 90 nm FPGA I/O buffer design with 1.6 Gbps data rate for source-synchronous system and 300 MHz clock rate for external memory interface.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
1998
Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, 1998
1995
Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process.
Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995