Bonita Bhaskaran

According to our database1, Bonita Bhaskaran authored at least 15 papers between 2005 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
ChipNeMo: Domain-Adapted LLMs for Chip Design.
CoRR, 2023

2022
On-Die Noise Measurement During Automatic Test Equipment (ATE) Testing and In-System-Test (IST).
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

Observation Point Insertion Using Deep Learning.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2020
A Novel Graph-Coloring-Based Solution for Low-Power Scan Shift.
IEEE Des. Test, 2020

2019
Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

An Efficient Supervised Learning Method to Predict Power Supply Noise During At-speed Test.
Proceedings of the IEEE International Test Conference, 2019

2017
At-speed capture global noise reduction & low-power memory test architecture.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016
A programmable method for low-power scan shift in SoC integrated circuits.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Test method and scheme for low-power validation in modern SOC integrated circuits.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Advanced test methodology for complex SoCs.
Proceedings of the 2016 IEEE International Test Conference, 2016

2007
DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Automated energy calculation and estimation for delay-insensitive digital circuits.
Microelectron. J., 2007

2005
High-Speed Energy Estimation for Delay-Insensitive Circuits.
Proceedings of the 2005 International Conference on Computer Design, 2005

Implementation of Design For Test for Asynchronous NCL Designs.
Proceedings of the 2005 International Conference on Computer Design, 2005

Fault Modeling and Testability of CMOS Domino Circuits.
Proceedings of the 2005 International Conference on Computer Design, 2005


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