Bon Woong Ku
Orcid: 0000-0001-9770-0297
According to our database1,
Bon Woong Ku
authored at least 21 papers
between 2015 and 2022.
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Bibliography
2022
Unsupervised Digit Recognition Using Cosine Similarity In A Neuromemristive Competitive Learning System.
ACM J. Emerg. Technol. Comput. Syst., 2022
ACM J. Emerg. Technol. Comput. Syst., 2022
2021
ACM Trans. Design Autom. Electr. Syst., 2021
ML-Based Wire RC Prediction in Monolithic 3D ICs with an Application to Full-Chip Optimization.
Proceedings of the ISPD '21: International Symposium on Physical Design, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs.
Proceedings of the ISPD 2020: International Symposium on Physical Design, Taipei, Taiwan, March 29, 2020
Pin-in-the-middle: an efficient block pin assignment methodology for block-level monolithic 3D ICs.
Proceedings of the ISLPED '20: ACM/IEEE International Symposium on Low Power Electronics and Design, 2020
2019
PhD thesis, 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
A Twin Memristor Synapse for Spike Timing Dependent Learning in Neuromorphic Systems.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018
Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs.
Proceedings of the 2018 International Symposium on Physical Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Design and architectural co-optimization of monolithic 3D liquid state machine-based neuromorphic processor.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Proceedings of the Neuromorphic Computing Symposium, 2017
Transistor-level monolithic 3D standard cell layout optimization for full-chip static power integrity.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Full-chip monolithic 3D IC design and power performance analysis with ASAP7 library: (Invited Paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
2015
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM.
Proceedings of the 52nd Annual Design Automation Conference, 2015