Bomy Chen

According to our database¹, Bomy Chen authored at least 11 papers between 2006 and 2019.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Bibliography

2019

Subsystem under 3D-Storage Class Memory on a chip.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2019

2017

Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

Erratum: CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction [IEICE Electronics Express Vol. 14 (2017) No. 10 pp. 20170053].

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

Multi-core architecture with asynchronous clocks to prevent power analysis attacks.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

2016

A 40-nm 16-Mb Contact-Programming Mask ROM Using Dual Trench Isolation Diode Bitcell.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

An FPGA enhanced extensible and parallel query storage system for emerging NVRAM.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2016

2007

Multilevel Storage in Phase-Change Memory.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2007

2006

Electronic properties of GST for non-volatile memory.

[BibT_eX]

[DOI]

Microelectron. J., 2006

Characterization of Ge2Sb2Te5 thin film transistor and its application in non-volatile memory.

[BibT_eX]

[DOI]

Microelectron. J., 2006

Bomy Chen

Timeline

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Bibliography

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