Bokyeon Won

According to our database1, Bokyeon Won authored at least 3 papers between 2024 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2025
A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration.
IEEE J. Solid State Circuits, January, 2025

2024
An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024



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