Bohan Yang

Orcid: 0000-0002-5204-1707

Affiliations:
  • Tsinghua University, Institute of Microelectronics, Beijing, China
  • K.U. Leuven, Belgium (former)


According to our database1, Bohan Yang authored at least 47 papers between 2014 and 2024.

Collaborative distances:

Timeline

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Bibliography

2024
Breaking Ground: A New Area Record for Low-Latency First-Order Masked SHA-3 Advancing from the 4x Area Era to the 3x Area Era.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

A Low-Latency High-Order Arithmetic to Boolean Masking Conversion.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

UpWB: An Uncoupled Architecture Design for White-box Cryptography Using Vectorized Montgomery Multiplication.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

Sparse Polynomial Multiplication-Based High-Performance Hardware Implementation for CRYSTALS-Dilithium.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

2023
A Closer Look at the Chaotic Ring Oscillators based TRNG Design.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023

A Low-Randomness First-Order Masked Xoodyak.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

2022
A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

CFNTT: Scalable Radix-2/4 NTT Multiplication Architecture with an Efficient Conflict-free Memory Mapping Scheme.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

Efficient FHE Radix-2 Arithmetic Operations Based on Redundant Encoding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An energy-efficient dynamically reconfigurable cryptographic engine with improved power/EM-side-channel-attack resistance.
Sci. China Inf. Sci., 2022

A SHA-512 Hardware Implementation Based on Block RAM Storage Structure.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Efficient access scheme for multi-bank based NTT architecture through conflict graph.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
LWRpro: An Energy-Efficient Configurable Crypto-Processor for Module-LWR.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Efficient Comparison and Addition for FHE With Weighted Computational Complexity Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

2020
Highly Efficient Architecture of NewHope-NIST on FPGA using Low-Complexity NTT/INTT.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020

Towards efficient and automated side-channel evaluations at design time.
J. Cryptogr. Eng., 2020

A High-performance Hardware Implementation of Saber Based on Karatsuba Algorithm.
IACR Cryptol. ePrint Arch., 2020

2018
ES-TRNG: A High-throughput, Low-area True Random Number Generator based on Edge Sampling.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

A Closer Look at the Delay-Chain based TRNG.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

The Impact of Pulsed Electromagnetic Fault Injection on True Random Number Generators.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018

Design and testing methodologies for true random number generators towards industry certification.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Towards inter-vendor compatibility of true random number generators for FPGAs.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Securing Wireless Neurostimulators.
Proceedings of the Eighth ACM Conference on Data and Application Security and Privacy, 2018

2017
Lightweight Prediction-Based Tests for On-Line Min-Entropy Estimation.
IEEE Embed. Syst. Lett., 2017

The Monte Carlo PUF.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Design of S-boxes Defined with Cellular Automata Rules.
Proceedings of the Computing Frontiers Conference, 2017

A Privacy-Preserving Device Tracking System Using a Low-Power Wide-Area Network.
Proceedings of the Cryptology and Network Security - 16th International Conference, 2017

On-chip jitter measurement for true random number generators.
Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016
Canary Numbers: Design for Light-weight Online Testability of True Random Number Generators.
IACR Cryptol. ePrint Arch., 2016

A Search Strategy to Optimize the Affine Variant Properties of S-Boxes.
Proceedings of the Arithmetic of Finite Fields - 6th International Workshop, 2016

Hold Your Breath, PRIMATEs Are Lightweight.
Proceedings of the Selected Areas in Cryptography - SAC 2016, 2016

On the Construction of Hardware-Friendly 4\times 4 and 5\times 5 S-Boxes.
Proceedings of the Selected Areas in Cryptography - SAC 2016, 2016

Evolving Cryptographic Pseudorandom Number Generators.
Proceedings of the Parallel Problem Solving from Nature - PPSN XIV, 2016

Exploring active manipulation attacks on the TERO random number generator.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

Iterating Von Neumann's post-processing under hardware constraints.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016


SOFIA: Software and control flow integrity architecture.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

TOTAL: TRNG on-the-fly testing for attack detection using Lightweight hardware.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

On the Feasibility of Cryptography for a Wireless Insulin Pump System.
Proceedings of the Sixth ACM on Conference on Data and Application Security and Privacy, 2016

PRNGs for Masking Applications and Their Mapping to Evolvable Hardware.
Proceedings of the Smart Card Research and Advanced Applications, 2016

Extreme Pipelining Towards the Best Area-Performance Trade-Off in Hardware.
Proceedings of the Progress in Cryptology - AFRICACRYPT 2016, 2016

2015
RECTANGLE: a bit-slice lightweight block cipher suitable for multiple platforms.
Sci. China Inf. Sci., 2015

On-the-fly tests for non-ideal true random number generators.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Challenges in designing trustworthy cryptographic co-processors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Embedded HW/SW platform for on-the-fly testing of true random number generators.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Highly efficient entropy extraction for true random number generators on FPGAs.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
RECTANGLE: A Bit-slice Ultra-Lightweight Block Cipher Suitable for Multiple Platforms.
IACR Cryptol. ePrint Arch., 2014


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