Bob Verbruggen
According to our database1,
Bob Verbruggen
authored at least 35 papers
between 2007 and 2021.
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Bibliography
2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
2019
Introduction to the Special Issue on the 2019 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2019
2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 7.4-to-14GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHz.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS.
IEEE J. Solid State Circuits, 2016
Digitally Modulated CMOS Polar Transmitters for Highly-Efficient mm-Wave Wireless Communication.
IEEE J. Solid State Circuits, 2016
2015
A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation.
IEEE J. Solid State Circuits, 2015
Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range".
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5<sup>th</sup>-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range.
IEEE J. Solid State Circuits, 2014
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration.
IEEE J. Solid State Circuits, 2014
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the ESSCIRC 2014, 2014
A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC.
Proceedings of the ESSCIRC 2014, 2014
2012
A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS.
IEEE J. Solid State Circuits, 2012
A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
IEEE J. Solid State Circuits, 2011
A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
2009
IEEE J. Solid State Circuits, 2009
IEEE J. Solid State Circuits, 2009
2008
IEEE J. Solid State Circuits, 2008
Advanced Planar Bulk and Multigate CMOS Technology: Analog-Circuit Benchmarking up to mm-Wave Frequencies.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007