Bob Rau

According to our database, Bob Rau authored at least 44 papers between 1976 and 2002.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2002

PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators.

Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman

J. VLSI Signal Process., 2002

Constructing and exploiting linear schedules with prescribed parallelism.

Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien

ACM Trans. Design Autom. Electr. Syst., 2002

PICO: Automatically Designing Custom Computers.

Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman

Computer, 2002

2001

Compiling for EPIC architectures.

Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau

Proc. IEEE, 2001

Embedded Computer Architecture and Automation.

B. Ramakrishna Rau, Michael S. Schlansker

Computer, 2001

2000

Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats.

Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau

ACM Trans. Design Autom. Electr. Syst., 2000

EPIC: Explicititly Parallel Instruction Computing.

Michael S. Schlansker, B. Ramakrishna Rau

Computer, 2000

A Constructive Solution to the Juggling Problem in Processor Array Synthesis.

Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien

Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000

Embedded Computing: New Directions in Architecture and Automation.

B. Ramakrishna Rau, Michael S. Schlansker

Proceedings of the High Performance Computing, 2000

The era of embedded computing.

B. Ramakrishna Rau

Proceedings of the 2000 International Conference on Compilers, 2000

Efficient design space exploration in PICO.

Santosh G. Abraham, B. Ramakrishna Rau

Proceedings of the 2000 International Conference on Compilers, 2000

High-Level Synthesis of Nonprogrammable Hardware Accelerators.

Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider

Proceedings of the 12th IEEE International Conference on Application-Specific Systems, 2000

1999

Machine-Description Driven Compilers for EPIC and VLIW Processors.

B. Ramakrishna Rau, Vinod Kathail, Shail Aditya

Des. Autom. Embed. Syst., 1999

Automatic Architectural Synthesis of VLIW and EPIC Processors.

Shail Aditya, B. Ramakrishna Rau, Vinod Kathail

Proceedings of the 12th International Symposium on System Synthesis, 1999

1998

Optimization of Machine Descriptions for Efficient Use.

John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau

Int. J. Parallel Program., 1998

1997

Region-based compilation: Introduction, motivation, and initial experience.

Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau

Int. J. Parallel Program., 1997

1996

Iterative Modulo Scheduling.

B. Ramakrishna Rau

Int. J. Parallel Program., 1996

Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks.

Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker

Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, 1996

1995

Region-based compilation: an introduction and motivation.

Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau

Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

1994

Iterative modulo scheduling: an algorithm for software pipelining loops.

B. Ramakrishna Rau

Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994

1993

Sentinel Scheduling for VLIW and Superscalar Processors.

Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker

ACM Trans. Comput. Syst., 1993

Instruction-level parallel processing: History, overview, and perspective.

B. Ramakrishna Rau, Joseph A. Fisher

J. Supercomput., 1993

Guest editors' introduction.

Joseph A. Fisher, B. Ramakrishna Rau

J. Supercomput., 1993

Reverse If-Conversion.

Nancy J. Warter, Scott A. Mahlke, Wen-mei W. Hwu, B. Ramakrishna Rau

Proceedings of the ACM SIGPLAN'93 Conference on Programming Language Design and Implementation (PLDI), 1993

Dynamically scheduled VLIW processors.

B. Ramakrishna Rau

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

Predictability of load/store instruction latencies.

Santosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. Ramakrishna Rau, Rajiv Gupta

Proceedings of the 26th Annual International Symposium on Microarchitecture, 1993

1992

Register Allocation for Software Pipelined Loops.

B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker

Proceedings of the ACM SIGPLAN'92 Conference on Programming Language Design and Implementation (PLDI), 1992

Code generation schema for modulo scheduled loops.

B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai

Proceedings of the 25th Annual International Symposium on Microarchitecture, 1992

Sentinel Scheduling for VLIW and Superscalar Processors.

Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker

Proceedings of the ASPLOS-V Proceedings, 1992

1991

Data Flow and Dependence Analysis for Instruction Level Parallelism.

B. Ramakrishna Rau

Proceedings of the Languages and Compilers for Parallel Computing, 1991

Pseudo-Randomly Interleaved Memory.

B. Ramakrishna Rau

Proceedings of the 18th Annual International Symposium on Computer Architecture. Toronto, 1991

1989

Appucations Development On the Very Long Instruction Word Cydra-5.

Peter Y.-T. Hsu, B. Ramakrishna Rau, K. J. M. Moriarty

Int. J. High Perform. Comput. Appl., 1989

The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs.

B. Ramakrishna Rau, David W. L. Yen, Wei C. Yen, Ross A. Towle

Computer, 1989

The Cydram 5 Stride-Insensitive Memory System.

B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen

Proceedings of the International Conference on Parallel Processing, 1989

1988

Cydra 5 Directed Dataflow Architecture.

B. Ramakrishna Rau

Proceedings of the COMPCON'88, Digest of Papers, Thirty-Third IEEE Computer Society International Conference, San Francisco, California, USA, February 29, 1988

1982

Efficient code generation for horizontal architectures: Compiler techniques and architectural support.

B. Ramakrishna Rau, Christopher D. Glaeser, Raymond L. Picard

Proceedings of the 9th International Symposium on Computer Architecture (ISCA 1982), 1982

Architectural Support for the Efficient Generation of Code for Horizontal Architectures.

B. Ramakrishna Rau, Christopher D. Glaeser, E. M. Greenawalt

Proceedings of the Symposium on Architectural Support for Programming Languages and Operating Systems, 1982

Systematically derived instruction sets for high-level language support.

Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker

Proceedings of the 20th Annual Southeast Regional Conference, 1982

1981

Some scheduling techniques and an easily schedulable horizontal architecture for high performance scientific computing.

B. Ramakrishna Rau, Christopher D. Glaeser

Proceedings of the 14th annual workshop on Microprogramming, 1981

1979

Program Behavior and the Performance of Interleaved Memories.

B. Ramakrishna Rau

IEEE Trans. Computers, 1979

Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System.

B. Ramakrishna Rau

IEEE Trans. Computers, 1979

1978

Levels of representation of programs and the architecture of universal host machines.

B. Ramakrishna Rau

Proceedings of the 11th annual workshop on Microprogramming, 1978

1977

The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units.

B. Ramakrishna Rau, George E. Rossman

Proceedings of the 4th Annual Symposium on Computer Architecture, 1977

1976

A new philosophy for interconnection on multilayer boards.

B. Ramakrishna Rau

Proceedings of the 13th Design Automation Conference, 1976