Bo Zhao

Affiliations:

University of Pittsburgh, Electrical and Computer Engineering Department, PA, USA (PhD 2013)

According to our database¹, Bo Zhao authored at least 19 papers between 2009 and 2015.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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On csauthors.net:

Bibliography

2015

Simple Virtual Channel Allocation for High-Throughput and High-Frequency On-Chip Routers.

[BibT_eX]

[DOI]

ACM Trans. Parallel Comput., 2015

Constructing Large and Fast On-Chip Cache for Mobile Processors with Multilevel Cell STT-MRAM Technology.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2015

2014

Throughput Enhancement for Phase Change Memories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

Errata to "Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor".

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

A low power and reliable charge pump design for Phase Change Memories.

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

2013

Common-source-line array: An area efficient memory architecture for bipolar nonvolatile devices.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Process Variation-Aware Nonuniform Cache Management in a 3D Die-Stacked Multicore Processor.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2013

A speculative arbiter design to enable high-frequency many-VC router in NoCs.

[BibT_eX]

[DOI]

Bo Zhao

Youtao Zhang

Jun Yang

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

2012

Improving write operations in MLC phase change memory.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012

Architecting a common-source-line array for bipolar non-volatile memory devices.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011

MRAC: A Memristor-based Reconfigurable Framework for Adaptive Cache Replacement.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010

Phase-Change Technology and the Future of Main Memory.

[BibT_eX]

[DOI]

IEEE Micro, 2010

2009

Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.

[BibT_eX]

[DOI]

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

A durable and energy efficient main memory using phase change memory technology.

[BibT_eX]

[DOI]

Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Energy reduction for STT-RAM using early write termination.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A low-radix and low-diameter 3D interconnection network design.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Frequent value compression in packet-based NoC architectures.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Bo Zhao

Timeline

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