Bo-Yi Chiang

According to our database, Bo-Yi Chiang authored at least 5 papers between 2006 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2008

Timing-constrained yield-driven redundant via insertion.

Jin-Tai Yan, Zhi-Wei Chen, Bo-Yi Chiang, Yu-Min Lee

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

Timing-Constrained Yield-Driven Wiring Reconstruction for Critical Area Minimization.

Jin-Tai Yan, Bo-Yi Chiang

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006

Timing-constrained yield-driven wire sizing for critical area minimization.

Jin-Tai Yan, Bo-Yi Chiang, Chia-Fang Lee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Yield-Driven Redundant Via Insertion Based on Probabilistic Via-Connection Analysis.

Jin-Tai Yan, Bo-Yi Chiang, Zhi-Wei Chen

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Width and Timing-Constrained Wire Sizing for Critical Area Minimization.

Jin-Tai Yan, Bo-Yi Chiang, Shi-Qin Huang

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006