Bo Yao

According to our database, Bo Yao authored at least 18 papers between 2001 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of two.

2011

On-Chip Interconnect Analysis of Performance and Energy Metrics Under Different Design Goals.

Ling Zhang, Yulei Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng

IEEE Trans. Very Large Scale Integr. Syst., 2011

2007

Efficient Timing Analysis With Known False Paths Using Biclique Covering.

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Repeated On-Chip Interconnect Analysis and Evaluation of Delay, Power, and Bandwidth Metrics under Different Design Goals.

Ling Zhang, Hongyu Chen, Bo Yao, Kevin Hamilton, Chung-Kuan Cheng

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006

Efficient static timing analysis using a unified framework for false paths and multi-cycle paths.

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

The Y architecture for on-chip interconnect: analysis and methodology.

Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Unified quadratic programming approach for mixed mode placement.

Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Lung-Tien Liu, Peter Suaris

Proceedings of the 2005 International Symposium on Physical Design, 2005

Improving the efficiency of static timing analysis with false paths.

Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Integrated algorithmic logical and physical design of integer multiplier.

Shuo Zhou, Bo Yao, Jianhua Liu, Chung-Kuan Cheng

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Floorplan Representation in VLSI.

Zhou Feng, Bo Yao, Chung-Kuan Cheng

Proceedings of the Handbook of Data Structures and Applications., 2004

A multiple level network approach for clock skew minimization with process variations.

Makoto Mori, Hongyu Chen, Bo Yao, Chung-Kuan Cheng

Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003

Floorplan representations: Complexity and connections.

Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham

ACM Trans. Design Autom. Electr. Syst., 2003

A hierarchical three-way interconnect architecture for hexagonal processors.

Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham

Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

Power network analysis using an adaptive algebraic multigrid approach.

Zhengyong Zhu, Bo Yao, Chung-Kuan Cheng

Proceedings of the 40th Design Automation Conference, 2003

An algebraic multigrid solver for analytical placement with layout based clustering.

Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu

Proceedings of the 40th Design Automation Conference, 2003

The Y-architecture: yet another on-chip interconnect solution.

Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Balancing the Interconnect Topology for Arrays of Processors between Cost and Power.

Esther Y. Cheng, Feng Zhou, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Physical Planning Of On-Chip Interconnect Architectures.

Hongyu Chen, Bo Yao, Feng Zhou, Chung-Kuan Cheng

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

Revisiting floorplan representations.

Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham

Proceedings of the 2001 International Symposium on Physical Design, 2001