Bo Yang
Affiliations:- Synopsys, Inc., Mountain View, CA, USA
- Design Algorithm Laboratory, Inc., Japan
- University of Kitakyushu, School of Environmental Engineering, Fukuoka, Japan (PhD 2009)
According to our database1,
Bo Yang
authored at least 22 papers
between 2008 and 2018.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2018
ACM Trans. Design Autom. Electr. Syst., 2018
2016
DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout.
ACM Trans. Design Autom. Electr. Syst., 2016
Routability of twisted common-centroid capacitor array under signal coupling constraints.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2013
Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
A comparator energy model considering shallow trench isolation stress by geometric programming.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013
2012
IEICE Trans. Electron., 2012
CMOS op-amp circuit synthesis with geometric programming models for layout-dependent effects.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Transistor channel decomposition for structured analog layout, manufacturability and low-power applications.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Layout-aware variation evaluation of analog circuits and its validity on op-amp designs.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011
2010
Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Structured analog circuit design and MOS transistor decomposition for high accuracy applications.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
2008
A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008