Bo Wang

According to our database, Bo Wang authored at least 21 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A 28-nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.

An Guo, Chen Xi, Fangyuan Dong, Xingyu Pu, Dongqi Li, Jingmin Zhang, Xueshan Dong, Hui Gao, Yiran Zhang, Bo Wang, Jun Yang, Xin Si

IEEE J. Solid State Circuits, September, 2024

Toggle Rate Aware Quantization Model Based on Digital Floating-Point Computing-In-Memory Architecture.

Xi Chen, Yitong Zhao, An Guo, Jinwu Chen, Fangyuan Dong, Zhaoyang Zhang, Tianzhu Xiong, Bo Wang, Yuyao Kong, Xin Si

IEEE Trans. Circuits Syst. II Express Briefs, June, 2024

34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.

An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A 28nm 16kb Aggregation and Combination Computing-in-Memory Macro with Dual-level Sparsity Modulation and Sparse-Tracking ADCs for GCNs.

Zhaoyang Zhang, Zhichao Liu, Feiran Liu, Yinhai Gao, Yuchen Ma, Yutong Zhang, An Guo, Tianzhu Xiong, Jinwu Chen, Xi Chen, Bo Wang, Yuchen Tang, Xingyu Pu, Xing Wang, Jun Yang, Xin Si

Proceedings of the IEEE Custom Integrated Circuits Conference, 2024

2023

From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits.

Zhaoyang Zhang, Jinwu Chen, Xi Chen, An Guo, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xingyu Pu, Shengnan He, Xin Si, Jun Yang

Sci. China Inf. Sci., October, 2023

Evaluation Model for Current-Domain SRAM-based Computing-in-Memory Circuits.

Yiran Zhang, Bo Wang, Jinwu Chen, Xi Chen, Xin Si

Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks.

Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.

An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

2022

SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation.

Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang, Xin Si

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

ShareFloat CIM: A Compute-In-Memory Architecture with Floating-Point Multiply-and-Accumulate Operations.

An Guo, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Chen Xue, Yufei Wang, Xin Si, Jun Yang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Booth-based Digital Compute-in-Memory Marco for Processing Transformer Model.

Zhongyuan Feng, Bo Wang, Zhaoyang Zhang, An Guo, Xin Si

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

Design Challenges and Methodology of High-Performance SRAM-Based Compute-in-Memory for AI Edge Devices.

Yufei Wang, Yongliang Zhou, Bo Wang, Tianzhu Xiong, Yuyao Kong, Xin Si

Proceedings of the International Conference on UK-China Emerging Technologies, 2021

Design Methodology towards High-Precision SRAM based Computation-in-Memory for AI Edge Devices.

Tianzhu Xiong, Yongliang Zhou, Yuyao Kong, Bo Wang, An Guo, Yufei Wang, Chen Xue, Haiming Hsu, Xin Si, Jun Yang

Proceedings of the 18th International SoC Design Conference, 2021

2020

A 60 Gb/s-Level Coarse-Grained Reconfigurable Cryptographic Processor With Less Than 1-W Power.

Chenchen Deng, Bo Wang, Leibo Liu, Min Zhu, Youyu Wu, Hui Li, Shouyi Yin, Shaojun Wei

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2019

Sandwich-RAM: An Energy-Efficient In-Memory BWN Architecture with Pulse-Width Modulation.

Jun Yang, Yuyao Kong, Zhen Wang, Yan Liu, Bo Wang, Shouyi Yin, Longxin Shi

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2018

Anole: A Highly Efficient Dynamically Reconfigurable Crypto-Processor for Symmetric-Key Algorithms.

Leibo Liu, Bo Wang, Chenchen Deng, Min Zhu, Shouyi Yin, Shaojun Wei

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

Exploration of Benes Network in Cryptographic Processors: A Random Infection Countermeasure for Block Ciphers Against Fault Attacks.

Bo Wang, Leibo Liu, Chenchen Deng, Min Zhu, Shouyi Yin, Zhuoquan Zhou, Shaojun Wei

IEEE Trans. Inf. Forensics Secur., 2017

2016

Against Double Fault Attacks: Injection Effort Model, Space and Time Randomization Based Countermeasures for Reconfigurable Array Architecture.

Bo Wang, Leibo Liu, Chenchen Deng, Min Zhu, Shouyi Yin, Shaojun Wei

IEEE Trans. Inf. Forensics Secur., 2016

Dynamically reconfigurable architecture for symmetric ciphers.

Bo Wang, Leibo Liu

Sci. China Inf. Sci., 2016

2015

A flexible and energy-efficient reconfigurable architecture for symmetric cipher processing.

Bo Wang, Leibo Liu

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography (Abstract Only).

Bo Wang, Leibo Liu

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015